TMS320F28335 Library  1.0
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Functions
general_input.h File Reference

Header file for General Input module. More...

Go to the source code of this file.

Functions

int16 init_generalInputPin (Uint16)
 Configuration of GPIO as general input pin. More...
 
int16 generalInputPin_getValue (Uint16)
 Configuration of GPIO as general input pin. More...
 
int16 generalInputPin_configureExternalInterrupt (Uint16, void *, Uint16)
 external interrupt on general input pin. More...
 
void generalInputPin_interruptAck ()
 Giving external interrupts acknowledge to interrupt again. More...
 

Detailed Description

Header file for General Input module.

Definition in file general_input.h.

Function Documentation

◆ generalInputPin_configureExternalInterrupt()

int16 generalInputPin_configureExternalInterrupt ( Uint16  pin,
void *  isr,
Uint16  edge 
)

external interrupt on general input pin.

Parameters
[in]1) GPIO pin as Uint16 --> valid value: 0-63 (see global_defines.h)
2) Interrupt Service routine
3) interrupt generation type (0=falling edge, 1=rising edge, 2=falling and rising edge)
Returns
Result of operations as int16
--> 0 = operation successful
--> -1 = invalid value of GPIO pin
--> -16 = invalid value of interrupt generation
--> -17 = all interrupts for GPIO range in use

Definition at line 91 of file general_input.c.

91  {
92  //make sure pin is configured as input pin first
93  static int Xint1_in_use=0;
94  static int Xint2_in_use=0;
95  static int Xint3_in_use=0;
96  static int Xint4_in_use=0;
97  static int Xint5_in_use=0;
98  static int Xint6_in_use=0;
99  static int Xint7_in_use=0;
100 
101  DINT; // Disable Interrupts
102  switch (pin){
103  case 0 ... 31: EALLOW; // Allow register-access
104  switch (pin){
105  case 0 ... 7: TMC_BASE_PIO->CTL[0].QSEL1 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
106  TMC_BASE_PIO->CTL[0].CTRL &= ~(0x3); // sampling period = Tsysclkout for GPIO
107  break;
108  case 8 ... 15: TMC_BASE_PIO->CTL[0].QSEL1 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
109  TMC_BASE_PIO->CTL[0].CTRL &= ~(0x3 << 8); // sampling period = Tsysclkout for GPIO
110  break;
111  case 16 ... 23: TMC_BASE_PIO->CTL[0].QSEL2 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
112  TMC_BASE_PIO->CTL[0].CTRL &= ~((Uint32)0x3 << 16); // sampling period = Tsysclkout for GPIO
113  break;
114  case 24 ... 31: TMC_BASE_PIO->CTL[0].QSEL2 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
115  TMC_BASE_PIO->CTL[0].CTRL &= ~((Uint32)0x3 << 24); // sampling period = Tsysclkout for GPIO
116  break;
117  default: EDIS;
118  return -1;
119  }
120  if(!Xint1_in_use){
121  TMC_BASE_INT_REGS->XINT1 = (Uint32)isr; // Register ISR in interrupt vector table
122  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
123  TMC_BASE_PIE->GROUP[0].IER |= 0x8; // Enable Xint1 in the PIE: Group 1 interrupt 4
124  IER |= (0x1); // Enable CPU Group int1
125  EINT; // Enable Global Interrupts
126 
127  TMC_BASE_PIO->XINT1SEL = pin; // Tag XINT1 interrupt with GPIO // Xint1 is GPIO 1
128 
129  switch(edge){
130  case 0: TMC_BASE_XINT->XINT1CR &= ~(0x3 << 2); // Interrupt generated on falling edge
131  break;
132  case 1: TMC_BASE_XINT->XINT1CR |= (0x1 << 2); // Interrupt generated on rising edge
133  break;
134  case 2: TMC_BASE_XINT->XINT1CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
135  break;
136  default: EDIS;
137  return -16; // Invalid value of interrupt generation
138  }
139 
140  TMC_BASE_XINT->XINT1CR |= 0x1; // Enable Interrupt
141  EDIS; // Protect Register
142  Xint1_in_use = 1; // Tag interrupt in use
143  }
144  else if(Xint1_in_use && (!Xint2_in_use)){
145  TMC_BASE_INT_REGS->XINT2 = (Uint32)isr; // Register ISR in interrupt vector table
146  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
147  TMC_BASE_PIE->GROUP[0].IER |= 0x10; // Enable Xint2 in the PIE: Group 1 interrupt 5
148  IER |= (0x1 << 0); // Enable CPU group int1
149  EINT; // Enable Global Interrupts
150 
151  TMC_BASE_PIO->XINT2SEL = pin; // Tag XINT2 interrupt with GPIO
152 
153  switch(edge){
154  case 0: TMC_BASE_XINT->XINT2CR &= ~(0x3 << 2); // Interrupt generated on falling edge
155  break;
156  case 1: TMC_BASE_XINT->XINT2CR |= (0x1 << 2); // Interrupt generated on rising edge
157  break;
158  case 2: TMC_BASE_XINT->XINT2CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
159  break;
160  default: EDIS;
161  return -16; // Invalid value of interrupt generation
162  }
163 
164  TMC_BASE_XINT->XINT2CR |= 0x1; // Enable Interrupt
165  EDIS;
166  Xint2_in_use = 1; // Tag interrupt in use
167  }
168  else{
169  EDIS;
170  return -17; // All interrupts of GPIO Range (0-31) in use
171  }
172  break;
173  case 32 ... 63: pin -= 32;
174  EALLOW; // Allow register-access
175  switch (pin){
176  case 0 ... 7: TMC_BASE_PIO->CTL[1].QSEL1 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
177  TMC_BASE_PIO->CTL[1].CTRL &= ~(0x3); // Sampling period = Tsysclkout for GPIO
178  break;
179  case 8 ... 15: TMC_BASE_PIO->CTL[1].QSEL1 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
180  TMC_BASE_PIO->CTL[1].CTRL &= ~(0x3 << 8); //Sampling period = Tsysclkout for GPIO
181  break;
182  case 16 ... 23: TMC_BASE_PIO->CTL[1].QSEL2 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
183  TMC_BASE_PIO->CTL[1].CTRL &= ~((Uint32)0x3 << 16); // Sampling period = Tsysclkout for GPIO
184  break;
185  case 24 ... 31: TMC_BASE_PIO->CTL[1].QSEL2 &= ~(0x3 << (pin*2)); // Synch to SYSCLKOUT only
186  TMC_BASE_PIO->CTL[1].CTRL &= ~((Uint32)0x3 << 24); // Sampling period = Tsysclkout for GPIO
187  break;
188  default: EDIS;
189  return -1;
190  }
191 
192 
193  if(!Xint3_in_use){
194  TMC_BASE_INT_REGS->XINT3 = (Uint32)isr; // Register ISR in interrupt vector table
195  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
196  TMC_BASE_PIE->GROUP[11].IER |= 0x1; // Enable Xint3 in the PIE: Group 12 interrupt 1
197  IER |= 0x0800; // Enable CPU group int 12
198  EINT; // Enable Global Interrupts
199 
200  TMC_BASE_PIO->XINT3SEL = pin; // Tag XINT3 interrupt with GPIO
201 
202  switch(edge){
203  case 0: TMC_BASE_XINT->XINT3CR &= ~(0x3 << 2); // Interrupt generated on falling edge
204  break;
205  case 1: TMC_BASE_XINT->XINT3CR |= (0x1 << 2); // Interrupt generated on rising edge
206  break;
207  case 2: TMC_BASE_XINT->XINT3CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
208  break;
209  default: EDIS;
210  return -16; // Invalid value of interrupt generation
211  }
212 
213  TMC_BASE_XINT->XINT3CR |= 0x1; // Enable Interrupt
214  EDIS;
215  Xint3_in_use = 1; // Tag interrupt in use
216  }
217  else if(Xint3_in_use && (!Xint4_in_use)){
218  TMC_BASE_INT_REGS->XINT4 = (Uint32)isr; // Register ISR in interrupt vector table
219  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
220  TMC_BASE_PIE->GROUP[11].IER |= 0x2; // Enable Xint4 in the PIE: Group 12 interrupt 2
221  IER |= 0x0800; // Enable CPU group int 12
222  EINT; // Enable Global Interrupts
223 
224  TMC_BASE_PIO->XINT4SEL = pin; // Tag XINT4 interrupt with GPIO
225 
226  switch(edge){
227  case 0: TMC_BASE_XINT->XINT4CR &= ~(0x3 << 2); // Interrupt generated on falling edge
228  break;
229  case 1: TMC_BASE_XINT->XINT4CR |= (0x1 << 2); // Interrupt generated on rising edge
230  break;
231  case 2: TMC_BASE_XINT->XINT4CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
232  break;
233  default: EDIS;
234  return -16; // Invalid value of interrupt generation
235  }
236 
237  TMC_BASE_XINT->XINT4CR |= 0x1; // Enable Interrupt
238  EDIS;
239  Xint4_in_use = 1; // Tag interrupt in use
240  }
241  else if(Xint3_in_use && Xint4_in_use && (!Xint5_in_use)){
242  TMC_BASE_INT_REGS->XINT5 = (Uint32)isr; // Register ISR in interrupt vector table
243  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
244  TMC_BASE_PIE->GROUP[11].IER |= 0x4; // Enable Xint5 in the PIE: Group 12 interrupt 3
245  IER |= 0x0800; // Enable CPU group int 12
246  EINT; // Enable Global Interrupts
247 
248  TMC_BASE_PIO->XINT5SEL = pin; // Tag XINT5 interrupt with GPIO
249 
250  switch(edge){
251  case 0: TMC_BASE_XINT->XINT5CR &= ~(0x3 << 2); // Interrupt generated on falling edge
252  break;
253  case 1: TMC_BASE_XINT->XINT5CR |= (0x1 << 2); // Interrupt generated on rising edge
254  break;
255  case 2: TMC_BASE_XINT->XINT5CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
256  break;
257  default: EDIS;
258  return -16; // Invalid value of interrupt generation
259  }
260 
261  TMC_BASE_XINT->XINT5CR |= 0x1; // Enable Interrupt
262  EDIS;
263  Xint5_in_use = 1; // Tag interrupt in use
264  }
265  else if(Xint3_in_use && Xint4_in_use && Xint5_in_use && (!Xint6_in_use)){
266  TMC_BASE_INT_REGS->XINT6 = (Uint32)isr; // Register ISR in interrupt vector table
267  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
268  TMC_BASE_PIE->GROUP[11].IER |= 0x8; // Enable Xint6 in the PIE: Group 12 interrupt 4
269  IER |= 0x0800; // Enable CPU group int 12
270  EINT; // Enable Global Interrupts
271 
272  TMC_BASE_PIO->XINT6SEL = pin; // Tag XINT6 interrupt with GPIO
273 
274  switch(edge){
275  case 0: TMC_BASE_XINT->XINT6CR &= ~(0x3 << 2); // Interrupt generated on falling edge
276  break;
277  case 1: TMC_BASE_XINT->XINT6CR |= (0x1 << 2); // Interrupt generated on rising edge
278  break;
279  case 2: TMC_BASE_XINT->XINT6CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
280  break;
281  default: EDIS;
282  return -16; // Invalid value of interrupt generation
283  }
284 
285  TMC_BASE_XINT->XINT6CR |= 0x1; // Enable Interrupt
286  EDIS;
287  Xint6_in_use = 1; // Tag interrupt in use
288  }
289  else if(Xint3_in_use && Xint4_in_use && Xint5_in_use && Xint6_in_use && (!Xint7_in_use)){
290  TMC_BASE_INT_REGS->XINT7 = (Uint32)isr; // Register ISR in interrupt vector table
291  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
292  TMC_BASE_PIE->GROUP[11].IER |= 0x10; // Enable Xint3 in the PIE: Group 12 interrupt 4
293  IER |= 0x0800; // Enable CPU group int 12
294  EINT; // Enable Global Interrupts
295 
296  TMC_BASE_PIO->XINT7SEL = pin; // Tag XINT7 interrupt with GPIO
297 
298  switch(edge){
299  case 0: TMC_BASE_XINT->XINT7CR &= ~(0x3 << 2); // Interrupt generated on falling edge
300  break;
301  case 1: TMC_BASE_XINT->XINT7CR |= (0x1 << 2); // Interrupt generated on rising edge
302  break;
303  case 2: TMC_BASE_XINT->XINT7CR |= (0x3 << 2); // Interrupt generated on rising and falling edge
304  break;
305  default: EDIS;
306  return -16; // Invalid value of interrupt generation
307  }
308 
309  TMC_BASE_XINT->XINT7CR |= 0x1; // Enable Interrupt
310  EDIS;
311  Xint7_in_use = 1; // Tag interrupt in use
312  }
313  else{
314  EDIS;
315  return -17; // All interrupts of GPIO Range (0-31) in use
316  }
317  break;
318  default: EDIS;
319  return -1;
320  }
321  return 0;
322 }

◆ generalInputPin_getValue()

int16 generalInputPin_getValue ( Uint16  pin)

Configuration of GPIO as general input pin.

Parameters
[in]1) GPIO pin as Uint16 --> valid value: 0-87 (see global_defines.h)
Returns
Result of operations as int16
--> 0 = value is 0 and operation successful
--> 1 = value is 1 and operation successful
--> -1 = invalid value of GPIO pin

Definition at line 67 of file general_input.c.

68 {
69  switch (pin){
70  case 0 ... 31: return ((TMC_BASE_PIO->DATA[0].DAT & ((Uint32)0x1 << pin)) >> pin);
71  case 32 ... 63: pin -= 32;
72  return ((TMC_BASE_PIO->DATA[1].DAT & ((Uint32)0x1 << pin)) >> pin);
73  case 64 ... 87: pin -= 64;
74  return ((TMC_BASE_PIO->DATA[2].DAT & ((Uint32)0x1 << pin)) >> pin);
75  default: return -1;
76  }
77 }

◆ generalInputPin_interruptAck()

void generalInputPin_interruptAck ( )

Giving external interrupts acknowledge to interrupt again.

Parameters
/
Returns
/

Definition at line 329 of file general_input.c.

329  {
330  TMC_BASE_PIE->ACK |= 0x801; // Acknowledge interrupt to get more ext. Interrupts
331 }

◆ init_generalInputPin()

int16 init_generalInputPin ( Uint16  pin)

Configuration of GPIO as general input pin.

Parameters
[in]1) GPIO pin as Uint16 --> valid value: 0-87 (see global_defines.h)
Returns
Result of operations as int16
--> 0 = operation successful
--> -1 = invalid value of GPIO pin

Definition at line 19 of file general_input.c.

20 {
21  EALLOW;
22  switch(pin){
23  case 0 ... 31: TMC_BASE_PIO->CTL[0].PUD |= ((Uint32)0x1 << pin); // Disable Pull-Up on GPIO
24  if(pin <= 15){
25  TMC_BASE_PIO->CTL[0].MUX1 &= ~((Uint32)0x3 << (pin*2)); // General purpose input/output
26  }
27  else{
28  TMC_BASE_PIO->CTL[0].MUX2 &= ~((Uint32)0x3 << ((pin-16)*2)); // General purpose input/output
29  }
30  TMC_BASE_PIO->CTL[0].DIR &= ~((Uint32)0x1 << pin); // Configures the GPIO pin as an input
31  break;
32  case 32 ... 63: pin -= 32;
33  TMC_BASE_PIO->CTL[1].PUD |= ((Uint32)0x1 << pin); // Disable Pull-Up on GPIO
34  if(pin <= 15){
35  TMC_BASE_PIO->CTL[1].MUX1 &= ~((Uint32)0x3 << (pin*2)); // General purpose input/output
36  }
37  else{
38  TMC_BASE_PIO->CTL[1].MUX2 &= ~((Uint32)0x3 << ((pin-16)*2)); // General purpose input/output
39  }
40  TMC_BASE_PIO->CTL[1].DIR &= ~((Uint32)0x1 << pin); // Configures the GPIO pin as an input
41  break;
42  case 64 ... 87: pin -= 64;
43  TMC_BASE_PIO->CTL[2].PUD |= ((Uint32)0x1 << pin); // Disable Pull-Up on GPIO
44  if(pin <=15){
45  TMC_BASE_PIO->CTL[2].MUX1 &= ~((Uint32)0x3 << (pin*2)); // General purpose input/output
46  }
47  else{
48  TMC_BASE_PIO->CTL[2].MUX2 &= ~((Uint32)0x3 << ((pin-16)*2)); // General purpose input/output
49  }
50  TMC_BASE_PIO->CTL[2].DIR &= ~((Uint32)0x1 << pin); // Configures the GPIO pin as an input
51  break;
52  default: EDIS;
53  return -1;
54  }
55  EDIS;
56  return 0;
57 }
IER
cregister volatile unsigned int IER
Generate reference to Interrupt Enable Register.
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22