TMS320F28335 Library  1.0
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sci.c
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1 
5 #include <register/TMC_BASE_INT_REGS.h>
6 #include <register/TMC_BASE_PIE.h>
7 #include <register/TMC_BASE_PIO.h>
8 #include <register/TMC_BASE_SCI.h>
9 #include "sci.h"
10 
21 int16 init_SCI(SCIInterface SCI_Int){
22  int BRR=0;
23  TMPS_SCI SCI; // Create variable for register-access
24  static int SCI_A_in_use=0;
25  static int SCI_B_in_use=0;
26  static int SCI_C_in_use=0;
27  EALLOW;
28  switch(SCI_Int.scirx){
29  case 11: if(!SCI_B_in_use){
30  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<11); // Enable Pullup for GPIO (SCIRXDB)
31  TMC_BASE_PIO->CTL[0].QSEL1 |= ((Uint32)0x3<<22); // Asynch input GPIO (SCIRXDB)
32  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<22); // Configure GPIO to SCIRXDB
33  switch(SCI_Int.scitx){
34  case 9: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<9); // Enable Pullup for GPIO (SCITXDB)
35  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<18); // Configure GPIO to SCITXDB
36  break;
37  case 14: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<14); // Enable Pullup for GPIO (SCITXDB)
38  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<28); // Configure GPIO to SCITXDB
39  break;
40  case 18: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<18); // Enable Pullup for GPIO (SCITXDB)
41  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x2<<4); // Configure GPIO to SCITXDB
42  break;
43  case 22: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<22); // Enable Pullup for GPIO (SCITXDB)
44  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x3<<12); // Configure GPIO to SCITXDB
45  break;
46  default: EDIS;
47  return -2;
48  }
49  SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
50  SCI_B_in_use=1;
51  break;
52  }
53  else{
54  return -10;
55  }
56  case 15: if(!SCI_B_in_use){
57  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<15); // Enable Pullup for GPIO (SCIRXDB)
58  TMC_BASE_PIO->CTL[0].QSEL1 |= ((Uint32)0x3<<30); // Asynch input GPIO (SCIRXDB)
59  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<30); // Configure GPIO to SCIRXDB
60  switch(SCI_Int.scitx){
61  case 9: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<9); // Enable Pullup for GPIO (SCITXDB)
62  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<18); // Configure GPIO to SCITXDB
63  break;
64  case 14: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<14); // Enable Pullup for GPIO (SCITXDB)
65  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<28); // Configure GPIO to SCITXDB
66  break;
67  case 18: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<18); // Enable Pullup for GPIO (SCITXDB)
68  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x2<<4); // Configure GPIO to SCITXDB
69  break;
70  case 22: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<22); // Enable Pullup for GPIO (SCITXDB)
71  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x3<<12); // Configure GPIO to SCITXDB
72  break;
73  default: EDIS;
74  return -2;
75  }
76  SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
77  SCI_B_in_use=1;
78  break;
79  }
80  else{
81  return -10;
82  }
83  case 19: if(!SCI_B_in_use){
84  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<19); // Enable Pullup for GPIO (SCIRXDB)
85  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<6); // Asynch input GPIO (SCIRXDB)
86  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x2<<6); // Configure GPIO to SCIRXDB
87  switch(SCI_Int.scitx){
88  case 9: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<9); // Enable Pullup for GPIO (SCITXDB)
89  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<18); // Configure GPIO to SCITXDB
90  break;
91  case 14: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<14); // Enable Pullup for GPIO (SCITXDB)
92  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<28); // Configure GPIO to SCITXDB
93  break;
94  case 18: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<18); // Enable Pullup for GPIO (SCITXDB)
95  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x2<<4); // Configure GPIO to SCITXDB
96  break;
97  case 22: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<22); // Enable Pullup for GPIO (SCITXDB)
98  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x3<<12); // Configure GPIO to SCITXDB
99  break;
100  default: EDIS;
101  return -2;
102  }
103  SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
104  SCI_B_in_use=1;
105  break;
106  }
107  else{
108  return -10;
109  }
110  case 23: if(!SCI_B_in_use){
111  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<23); // Enable Pullup for GPIO (SCIRXDB)
112  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<14); // Asynch input GPIO (SCIRXDB)
113  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x3<<14); // Configure GPIO to SCIRXDB
114  switch(SCI_Int.scitx){
115  case 9: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<9); // Enable Pullup for GPIO (SCITXDB)
116  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<18); // Configure GPIO to SCITXDB
117  break;
118  case 14: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<14); // Enable Pullup for GPIO (SCITXDB)
119  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2<<28); // Configure GPIO to SCITXDB
120  break;
121  case 18: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<18); // Enable Pullup for GPIO (SCITXDB)
122  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x2<<4); // Configure GPIO to SCITXDB
123  break;
124  case 22: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<22); // Enable Pullup for GPIO (SCITXDB)
125  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x3<<12); // Configure GPIO to SCITXDB
126  break;
127  default: EDIS;
128  return -2;
129  }
130  SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
131  SCI_B_in_use=1;
132  break;
133  }
134  else{
135  return -10;
136  }
137  case 28: if(!SCI_A_in_use){
138  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<28); // Enable Pullup for GPIO (SCIRXDA)
139  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<24); // Asynch input GPIO (SCIRXDA)
140  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1<<24); // Configure GPIO to SCIRXDA
141  switch(SCI_Int.scitx){
142  case 29: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<29); // Enable Pullup for GPIO (SCITXDB)
143  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1<<26); // Configure GPIO29 to SCITXDA
144  break;
145  default: EDIS;
146  return -2;
147  }
148  SCI=TMC_BASE_SCIA; // Assign Register-address to variable for register access
149  SCI_A_in_use=1;
150  break;
151  }
152  else{
153  return -10;
154  }
155  case 62: if(!SCI_C_in_use){
156  TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<30); // Enable Pullup for GPIO (SCIRXDC)
157  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<28); // Asynch input GPIO (SCIRXDC)
158  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<28); // Configure GPIO to SCIRXDC
159  switch(SCI_Int.scitx){
160  case 63: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<31); // Enable Pullup for GPIO (SCITXDB)
161  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<30); // Configure GPIO63 to SCITXDC
162  break;
163  default: EDIS;
164  return -2;
165  }
166  SCI=TMC_BASE_SCIC; // Assign Register-address to variable for register access
167  SCI_C_in_use=1;
168  break;
169  }
170  else{
171  return -10;
172  }
173  default: EDIS;
174  return -1;
175  }
176  EDIS;
177 
178  SCI->CCR |= (0x7); // Char-Length: 8 Bits
179  SCI->CTL1 |= (0x1); // SCI receiver enabled
180  SCI->CTL1 |= (0x1 << 1); // SCI transmitter enabled
181  SCI->PRI |= (0x1 << 3); // Complete current receive/tansmit sequence before stop on break
182  BRR = (0x23BE000/((long)SCI_Int.baudrate*8))-1; // Calculate baud rate
183 
184  SCI->HBAUD = BRR >> 8; // Configure baud rate
185  SCI->LBAUD = BRR&0xFF; // Configure baud rate
186 
187  SCI->FFTX |= ((Uint32)0x1 << 14); // FIFO enabled
188  SCI->FFTX |= ((Uint32)0x1 << 13); // FIFO enabled
189  SCI->FFTX |= (0x1 << 5); // Transmit FIFO interrupt enable
190  SCI->FFTX |= (0x1 << 6); // Transmit FIFO interrupt clear
191  SCI->FFTX &= ~(0x1F); // Transmit FIFO interrupt when Transmit Fifo empty
192 
193  SCI->FFRX |= (0x1 << 14); // Receive FIFO overflow clear
194  SCI->FFRX |= (0x1 << 13); // Enable Receive FIFO
195  SCI->FFRX |= (0x1 << 5); // Receive FIFO interrupt enable
196  SCI->FFRX &= ~(0x1F);
197  SCI->FFRX |= (0x1); // Receive FIFO interrupt when there are 1 or more words in receive fifo
198  SCI->FFRX |= (0x1 << 6); // Receive FIFO interrupt clear
199 
200  SCI->CTL1 |= (0x1<<5); // Enable SCI
201 
202  return 0;
203 }
204 
213 int16 SCI_setInterruptTx(SCIInterface SCI_Int, void * spiTxFIFOISR){
214  DINT; // Disable Interrupts
215  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
216  EALLOW; // Allow register access
217  switch(SCI_Int.scitx){
218  case 9: TMC_BASE_INT_REGS->SCITXINTB_SCI = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
219  TMC_BASE_PIE->GROUP[8].IER |= 0x8; // Enable SCITXINTB_SCI in the PIE: Group 9 interrupt 4
220  IER |= 0x0100;
221  break;
222  case 14: TMC_BASE_INT_REGS->SCITXINTB_SCI = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
223  TMC_BASE_PIE->GROUP[8].IER |= 0x8; // Enable SCITXINTB_SCI in the PIE: Group 9 interrupt 4
224  IER |= 0x0100;
225  break;
226  case 18: TMC_BASE_INT_REGS->SCITXINTB_SCI = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
227  TMC_BASE_PIE->GROUP[8].IER |= 0x8; // Enable SCITXINTB_SCI in the PIE: Group 9 interrupt 4
228  IER |= 0x0100;
229  break;
230  case 22: TMC_BASE_INT_REGS->SCITXINTB_SCI = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
231  TMC_BASE_PIE->GROUP[8].IER |= 0x8; // Enable SCITXINTB_SCI in the PIE: Group 9 interrupt 4
232  IER |= 0x0100;
233  break;
234  case 29: TMC_BASE_INT_REGS->SCITXINTA_SCI = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
235  TMC_BASE_PIE->GROUP[8].IER |= 0x2; // Enable SCITXINTA_SCI in the PIE: Group 9 interrupt 2
236  IER |= 0x0100;
237  break;
238  case 63: TMC_BASE_INT_REGS->SCITXINTC_SCI = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
239  TMC_BASE_PIE->GROUP[7].IER |= 0x20; // Enable SCITXINTC_SCI in the PIE: Group 8 interrupt 6
240  IER |= 0x0080;
241  break;
242  default: EINT; // Enable Interrupts
243  EDIS; // Protect Register
244  return -1;
245  }
246  EINT;
247  EDIS;
248  return 0;
249 }
250 
259 int16 SCI_setInterruptRx(SCIInterface SCI_Int, void * spiRxFIFOISR){
260  DINT; // Disable Interrupts
261  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
262  EALLOW; // Allow register access
263  switch(SCI_Int.scirx){
264  case 11: TMC_BASE_INT_REGS->SCIRXINTB_SCI = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
265  TMC_BASE_PIE->GROUP[8].IER |= 0x4; // Enable SCIRXINTB_SCI in the PIE: Group 9 interrupt 3
266  IER |= 0x0100;
267  break;
268  case 15: TMC_BASE_INT_REGS->SCIRXINTB_SCI = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
269  TMC_BASE_PIE->GROUP[8].IER |= 0x4; // Enable SCIRXINTB_SCI in the PIE: Group 9 interrupt 3
270  IER |= 0x0100;
271  break;
272  case 19: TMC_BASE_INT_REGS->SCIRXINTB_SCI = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
273  TMC_BASE_PIE->GROUP[8].IER |= 0x4; // Enable SCIRXINTB_SCI in the PIE: Group 9 interrupt 3
274  IER |= 0x0100;
275  break;
276  case 23: TMC_BASE_INT_REGS->SCIRXINTB_SCI = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
277  TMC_BASE_PIE->GROUP[8].IER |= 0x4; // Enable SCIRXINTB_SCI in the PIE: Group 9 interrupt 3
278  IER |= 0x0100;
279  break;
280  case 28: TMC_BASE_INT_REGS->SCIRXINTA_SCI = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
281  TMC_BASE_PIE->GROUP[8].IER |= 0x1; // Enable SCIRXINTA_SCI in the PIE: Group 9 interrupt 3
282  IER |= 0x0100;
283  break;
284  case 62: TMC_BASE_INT_REGS->SCIRXINTC_SCI = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
285  TMC_BASE_PIE->GROUP[7].IER |= 0x10; // Enable SCIRXINTC_SCI in the PIE: Group 8 interrupt 5
286  IER |= 0x0080;
287  break;
288  default: EINT; // Enable Interrupts
289  EDIS; // Protect Register
290  return -1;
291  }
292  EDIS;
293  EINT;
294  return 0;
295 }
296 
305 int16 SCI_send(SCIInterface SCI_Int, Uint8 data){
306  TMPS_SCI SCI; // Create variable for register-access
307  switch(SCI_Int.scitx){
308  case 9: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
309  break;
310  case 14: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
311  break;
312  case 18: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
313  break;
314  case 22: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
315  break;
316  case 29: SCI=TMC_BASE_SCIA; // Assign Register-address to variable for register access
317  break;
318  case 63: SCI=TMC_BASE_SCIC; // Assign Register-address to variable for register access
319  break;
320  default: return -1;
321  }
322  SCI->TXBUF=data; // Write data to TXBUF
323  return 0;
324 }
325 
334 int16 SCI_read(SCIInterface SCI_Int, Uint8 *data) {
335  TMPS_SCI SCI; // Create variable for register-access
336  switch(SCI_Int.scirx){
337  case 11: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
338  break;
339  case 15: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
340  break;
341  case 19: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
342  break;
343  case 23: SCI=TMC_BASE_SCIB; // Assign Register-address to variable for register access
344  break;
345  case 28: SCI=TMC_BASE_SCIA; // Assign Register-address to variable for register access
346  break;
347  case 62: SCI=TMC_BASE_SCIC; // Assign Register-address to variable for register access
348  break;
349  default: return -1;
350  }
351 
352  if(SCI->FFRX & 0x1F00){ // If Data in RXBUF
353  *data = SCI->RXBUF; // Read Data
354  }
355  return 0;
356 }
357 
363 void SCI_clearRxInterruptFlag(SCIInterface SCI_Int){
364  TMPS_SCI SCI;
365  switch(SCI_Int.scirx){
366  case 11: SCI=TMC_BASE_SCIB;
367  break;
368  case 15: SCI=TMC_BASE_SCIB;
369  break;
370  case 19: SCI=TMC_BASE_SCIB;
371  break;
372  case 23: SCI=TMC_BASE_SCIB;
373  break;
374  case 28: SCI=TMC_BASE_SCIA;
375  break;
376  case 62: SCI=TMC_BASE_SCIC;
377  break;
378  default: break;
379  }
380  SCI->FFRX |= (0x1<<6); //clear int
381 }
382 
388 void SCI_clearTxInterruptFlag(SCIInterface SCI_Int){
389  TMPS_SCI SCI;
390  switch(SCI_Int.scirx){
391  case 11: SCI=TMC_BASE_SCIB;
392  break;
393  case 15: SCI=TMC_BASE_SCIB;
394  break;
395  case 19: SCI=TMC_BASE_SCIB;
396  break;
397  case 23: SCI=TMC_BASE_SCIB;
398  break;
399  case 28: SCI=TMC_BASE_SCIA;
400  break;
401  case 62: SCI=TMC_BASE_SCIC;
402  break;
403  default: break;
404  }
405  SCI->FFTX |= (0x1<<6); //clear int
406 }
407 
413 void SCI_interruptAck(){
414  TMC_BASE_PIE->ACK |= 0x180; // Acknowledge interrupt to get more from group all interrupt groups
415 }
416 
417 
_SCIInterface::scitx
Uint16 scitx
SCI-Tx-GPIO for Transmit operation.
Definition: sci.h:11
TMC_BASE_PIE.h
PIE-Register header file.
_TMS_SCI::RXBUF
TM_REG16 RXBUF
Receive Data Buffer Register.
Definition: TMC_BASE_SCI.h:23
int16
int int16
16 Bit Variable: - 32.768 .. 32.767
Definition: global_defines.h:17
_TMS_SCI::PRI
TM_REG16 PRI
Priority Control Register.
Definition: TMC_BASE_SCI.h:30
IER
cregister volatile unsigned int IER
Generate reference to Interrupt Enable Register.
_SCIInterface
SCI Interface: Assign GPIOs and baudrate to SCI_A / SCI_B / SCI_C.
Definition: sci.h:9
_TMS_SCI
SCI Register (TMC_BASE_SCIA / TMC_BASE_SCIB / TMC_BASE_SCIC).
Definition: TMC_BASE_SCI.h:15
sci.h
Header file for SCI module.
_TMS_SCI::CCR
TM_REG16 CCR
Communications Control Register.
Definition: TMC_BASE_SCI.h:16
SCI_send
int16 SCI_send(SCIInterface SCI_Int, Uint8 data)
SCI Interface Send data to Tx FIFO.
Definition: sci.c:305
_SCIInterface::baudrate
Uint32 baudrate
SCI-baudrate for receive and transmit operation.
Definition: sci.h:12
_TMS_SCI::FFTX
TM_REG16 FFTX
FIFO Transmit Register.
Definition: TMC_BASE_SCI.h:26
SCI_read
int16 SCI_read(SCIInterface SCI_Int, Uint8 *data)
SCI Interface Read data from Rx FIFO.
Definition: sci.c:334
TMC_BASE_SCI.h
SCI-Register header file.
SCI_clearRxInterruptFlag
void SCI_clearRxInterruptFlag(SCIInterface SCI_Int)
SCI Interface clear Rx Interrupt flag.
Definition: sci.c:363
SCI_setInterruptTx
int16 SCI_setInterruptTx(SCIInterface SCI_Int, void *spiTxFIFOISR)
Configure Tx Interrupt of SCI Interface.
Definition: sci.c:213
_TMS_SCI::LBAUD
TM_REG16 LBAUD
Baud Register, Low Bits.
Definition: TMC_BASE_SCI.h:19
init_SCI
int16 init_SCI(SCIInterface SCI_Int)
Initialization of SCI Interface.
Definition: sci.c:21
_TMS_SCI::TXBUF
TM_REG16 TXBUF
Transmit Data Buffer Register.
Definition: TMC_BASE_SCI.h:25
_TMS_SCI::HBAUD
TM_REG16 HBAUD
Baud Register, High Bits.
Definition: TMC_BASE_SCI.h:18
_TMS_SCI::FFRX
TM_REG16 FFRX
FIFO Receive Register.
Definition: TMC_BASE_SCI.h:27
TMC_BASE_INT_REGS.h
Interupt-Register header file.
Uint8
unsigned char Uint8
8 Bit Variable: 0 .. 255
Definition: global_defines.h:20
SCI_clearTxInterruptFlag
void SCI_clearTxInterruptFlag(SCIInterface SCI_Int)
SCI Interface clear Tx Interrupt flag.
Definition: sci.c:388
_SCIInterface::scirx
Uint16 scirx
SCI-Rx-GPIO for Receive operation.
Definition: sci.h:10
SCI_setInterruptRx
int16 SCI_setInterruptRx(SCIInterface SCI_Int, void *spiRxFIFOISR)
Configure Rx Interrupt of SCI Interface.
Definition: sci.c:259
TMC_BASE_PIO.h
GPIO-Register header file.
SCI_interruptAck
void SCI_interruptAck()
Giving interrupts acknowledge to interrupt again.
Definition: sci.c:413
_TMS_SCI::CTL1
TM_REG16 CTL1
Control Register 1.
Definition: TMC_BASE_SCI.h:17
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22