adc.h File Reference

Header file for ADC module. More...

Go to the source code of this file.

Functions
void	init_ADC (void)
	Init ADC. More...
int16	ADC_getValue (Uint16)
	Get Value of ADCIN-Pin. More...

Detailed Description

Header file for ADC module.

Definition in file adc.h.

Function Documentation

ADC_getValue()

int16 ADC_getValue

(

Uint16

adc_pin

)

Get Value of ADCIN-Pin.

Parameters

[in]

1) adc_pin --> valid value:ADCINA0-ADCINB7

Returns

Result of operations as int16
--> 0-4095 = operation successful --> value of ADCRESULT-Register
--> -1 = invalid value of adc_pin

Definition at line 56 of file adc.c.

                                  {
    switch(adc_pin){
    case 0 ... 15:  TMC_BASE_ADC->TRL2 = 0x2000;                        // Start-of-conversion
                    __asm(" RPT #255 || NOP");                          // Wait for conversion
                    return (TMC_BASE_ADC_RESULT->RESULT[adc_pin]);      // Return result value (0-4095)
    default:        return -1;
    }
}

init_ADC()

void init_ADC

(

void

)

Init ADC.

Parameters

[in]

/

Returns

/

Definition at line 16 of file adc.c.

               {
    int i=0;
 
    // Define ADCCLK clock frequency ( less than or equal to 25 MHz )
    EALLOW;                                 // Allow register writes
    TMC_BASE_SCR->HISPCP = 0x3;             // Set High-Speed Peripheral Clock Prescaler to 3 for High speed clock = SYSCLKOUT/6
    (*ADC_Cal) ();                          // ADCREFSEL and ADCOFFTRIM must be initialized
    EDIS;                                   // protect register
 
    __asm(" RPT #10 || NOP");               // Provides the required delay between writes to ADCTRL1
 
    TMC_BASE_ADC->TRL1 |= (0x1 << 4);       // Setup cascaded sequencer mode
    TMC_BASE_ADC->TRL3 |= (0x1);            // Setup simultaneous sampling mode
    TMC_BASE_ADC->MAXCONV |= (0x0007);      // 8 double conv's (16 total)
 
    TMC_BASE_ADC->CHSELSEQ1 &= ~(0xF);      // Setup conv from channels ADCINA0 and ADCINB0
    TMC_BASE_ADC->CHSELSEQ1 |= (0x1 << 4);  // Setup conv from channels ADCINA1 and ADCINB1
    TMC_BASE_ADC->CHSELSEQ1 |= (0x2 << 8);  // Setup conv from channels ADCINA2 and ADCINB2
    TMC_BASE_ADC->CHSELSEQ1 |= (0x3 << 12); // Setup conv from channels ADCINA3 and ADCINB3
    TMC_BASE_ADC->CHSELSEQ2 |= (0x4);       // Setup conv from channels ADCINA4 and ADCINB4
    TMC_BASE_ADC->CHSELSEQ2 |= (0x5 << 4);  // Setup conv from channels ADCINA5 and ADCINB5
    TMC_BASE_ADC->CHSELSEQ2 |= (0x6 << 8);  // Setup conv from channels ADCINA6 and ADCINB6
    TMC_BASE_ADC->CHSELSEQ2 |= (0x7 << 12); // Setup conv from channels ADCINA7 and ADCINB7
 
    TMC_BASE_ADC->TRL3 |= 0x00E0;            // Power up ADC circuits
 
    for(i=0; i<3000; i++){
        __asm(" RPT #255 || NOP");          // Provides the required delay of 5ms
    }
 
    TMC_BASE_ADC->TRL2 = 0x2000;            // Start-of-conversion
}