TMS320F28335 Library  1.0
Documentation
ecap.c
Go to the documentation of this file.
1 
6 #include "global_defines.h"
7 #include <register/TMC_BASE_ECAP.h>
8 #include <register/TMC_BASE_INT_REGS.h>
9 #include <register/TMC_BASE_PIE.h>
10 #include <register/TMC_BASE_PIO.h>
11 #include "ecap.h"
12 
13 //Interrupt Service Routines Function-Declarations
14 __interrupt void eCAP1_isr(void);
15 __interrupt void eCAP2_isr(void);
16 __interrupt void eCAP3_isr(void);
17 __interrupt void eCAP4_isr(void);
18 __interrupt void eCAP5_isr(void);
19 __interrupt void eCAP6_isr(void);
20 
21 //global Variables for eCAP-values
22 Uint32 g_time_ecap1=0;
23 Uint32 g_time_ecap2=0;
24 Uint32 g_time_ecap3=0;
25 Uint32 g_time_ecap4=0;
26 Uint32 g_time_ecap5=0;
27 Uint32 g_time_ecap6=0;
28 
29 //global Variables for usage-flags
30 static int g_ecap1_in_use=0;
31 static int g_ecap2_in_use=0;
32 static int g_ecap3_in_use=0;
33 static int g_ecap4_in_use=0;
34 static int g_ecap5_in_use=0;
35 static int g_ecap6_in_use=0;
36 
45 int16 init_eCAP(Uint16 gpio){
46  TMPS_ECAP ECAP; // Create variable for register-access
47  switch(gpio){
48  case 1: if(!g_ecap6_in_use){
49  g_ecap6_in_use = 1; // Configuring GPIO as eCAP6
50  EALLOW; // Allow register-access
51  TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << 1); // Enable pull-up on GPIO1 (CAP6)
52  TMC_BASE_PIO->CTL[0].QSEL1 &= ~((Uint32)0x3 << 2); // Synch to SYSCLKOUT GPIO1 (CAP6)
53  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2 << 2); // Configure GPIO1 as CAP6
54  ECAP = TMC_BASE_ECAP6; // Assign Register-address to variable for register access
55  eCAP_configureInterrupt(gpio, &eCAP6_isr, 4); // Configure GPIO1 to call ISR on Capture Event 1
56  EDIS; // Protect register
57  break;
58  }
59  else{
60  return -10; // eCAP6 already in use
61  }
62  case 3: if(!g_ecap5_in_use){
63  g_ecap5_in_use = 1; // Configuring GPIO3 as eCAP5
64  EALLOW; // Allow register-access
65  TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << 3); // Enable pull-up on GPIO3 (CAP5)
66  TMC_BASE_PIO->CTL[0].QSEL1 &= ~((Uint32)0x3 << 6); // Synch to SYSCLKOUT GPIO3 (CAP5)
67  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x2 << 6); // Configure GPIO3 as CAP5
68  ECAP = TMC_BASE_ECAP5; // Assign Register-address to variable for register access
69  eCAP_configureInterrupt(gpio, &eCAP5_isr, 4); // Configure GPIO3 to call ISR on Capture Event 1
70  EDIS; // Protect register
71  break;
72  }
73  else{
74  return -10; // eCAP5 already in use
75  }
76  case 5: if(!g_ecap1_in_use){
77  g_ecap1_in_use = 1; // Configuring GPIO5 as eCAP1
78  EALLOW; // Allow register-access
79  TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << 5); // Enable pull-up on GPIO5 (CAP1)
80  TMC_BASE_PIO->CTL[0].QSEL1 &= ~((Uint32)0x3 << 10); // Synch to SYSCLKOUT GPIO5 (CAP1)
81  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x3 << 10); // Configure GPIO5 as CAP1
82  ECAP = TMC_BASE_ECAP1; // Assign Register-address to variable for register access
83  eCAP_configureInterrupt(gpio, &eCAP1_isr, 1); // Configure GPIO5 to call ISR on Capture Event 1
84  EDIS; // Protect register
85  break;
86  }
87  else{
88  return -10; // eCAP1 already in use
89  }
90  case 7: if(!g_ecap2_in_use){
91  g_ecap2_in_use = 1; // Configuring GPIO7 as eCAP2
92  EALLOW; // Allow register-access
93  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << 7); // Enable pull-up on GPIO7 (CAP2)
94  TMC_BASE_PIO->CTL[0].QSEL1 &= ~((Uint32)0x3 << 14); // Synch to SYSCLKOUT GPIO7 (CAP2)
95  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x3 << 14); // Configure GPIO7 as CAP2
96  ECAP = TMC_BASE_ECAP2; // Assign Register-address to variable for register access
97  eCAP_configureInterrupt(gpio, &eCAP2_isr, 4); // Configure GPIO7 to call ISR on Capture Event 1
98  EDIS; // Protect register
99  break;
100  }
101  else{
102  return -10; // eCAP2 already in use
103  }
104  case 9: if(!g_ecap3_in_use){
105  g_ecap3_in_use = 1; // Configuring GPIO9 as eCAP3
106  EALLOW; // Allow register-access
107  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << 9); // Enable pull-up on GPIO9 (CAP3)
108  TMC_BASE_PIO->CTL[0].QSEL1 &= ~((Uint32)0x3 << 18); // Synch to SYSCLKOUT GPIO9 (CAP3)
109  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x3 << 18); // Configure GPIO9 as CAP3
110  ECAP = TMC_BASE_ECAP3; // Assign Register-address to variable for register access
111  eCAP_configureInterrupt(gpio, &eCAP3_isr, 4); // Configure GPIO9 to call ISR on Capture Event 1
112  EDIS; // Protect register
113  break;
114  }
115  else{
116  return -10; // eCAP3 already in use
117  }
118  case 11: if(!g_ecap4_in_use){
119  g_ecap4_in_use = 1; // Configuring GPIO11 as eCAP4
120  EALLOW; // Allow register-access
121  TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << 11); // Enable pull-up on GPIO11 (CAP4)
122  TMC_BASE_PIO->CTL[0].QSEL1 &= ~((Uint32)0x3 << 22); // Synch to SYSCLKOUT GPIO11 (CAP4)
123  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x3 << 22); // Configure GPIO11 as CAP4
124  ECAP = TMC_BASE_ECAP4; // Assign Register-address to variable for register access
125  eCAP_configureInterrupt(gpio, &eCAP4_isr, 4); // Configure GPIO11 to call ISR on Capture Event 1
126  EDIS; // Protect register
127  break;
128  }
129  else{
130  return -10; // eCAP4 already in use
131  }
132  case 24: if(!g_ecap1_in_use){
133  g_ecap1_in_use = 1; // Configuring GPIO24 as eCAP1
134  EALLOW; // Allow register-access
135  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << 24); // Enable pull-up on GPIO24 (CAP1)
136  TMC_BASE_PIO->CTL[0].QSEL2 &= ~((Uint32)0x3 << 16); // Synch to SYSCLKOUT GPIO24 (CAP1)
137  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1 << 16); // Configure GPIO24 as CAP1
138  ECAP = TMC_BASE_ECAP1; // Assign Register-address to variable for register access
139  eCAP_configureInterrupt(gpio, &eCAP1_isr, 4); // Configure GPIO24 to call ISR on Capture Event 1
140  EDIS; // Protect register
141  break;
142  }
143  else{
144  return -10; // eCAP1 already in use
145  }
146  case 25: if(!g_ecap2_in_use){
147  g_ecap2_in_use = 1; // Configuring GPIO25 as eCAP2
148  EALLOW; // Allow register-access
149  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << 25); // Enable pull-up on GPIO25 (CAP2)
150  TMC_BASE_PIO->CTL[0].QSEL2 &= ~((Uint32)0x3 << 18); //Synch to SYSCLKOUT GPIO25 (CAP2)
151  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1 << 18); // Configure GPIO25 as CAP2
152  ECAP = TMC_BASE_ECAP2; // Assign Register-address to variable for register access
153  eCAP_configureInterrupt(gpio, &eCAP2_isr, 4); // Configure GPIO25 to call ISR on Capture Event 1
154  EDIS; // Protect register
155  break;
156  }
157  else{
158  return -10; // eCAP2 already in use
159  }
160  case 26: if(!g_ecap3_in_use){
161  g_ecap3_in_use = 1; // Configuring GPIO26 as eCAP3
162  EALLOW; // Allow register-access
163  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << 26); // Enable pull-up on GPIO26 (CAP3)
164  TMC_BASE_PIO->CTL[0].QSEL2 &= ~((Uint32)0x3 << 20); // Synch to SYSCLKOUT GPIO26 (CAP3)
165  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1 << 20); // Configure GPIO26 as CAP3
166  ECAP = TMC_BASE_ECAP3; // Assign Register-address to variable for register access
167  eCAP_configureInterrupt(gpio, &eCAP3_isr, 4); // Configure GPIO26 to call ISR on Capture Event 1
168  EDIS; // Protect register
169  break;
170  }
171  else{
172  return -10; // eCAP3 already in use
173  }
174  case 27: if(!g_ecap4_in_use){
175  g_ecap4_in_use = 1; // Configuring GPIO27 as eCAP4
176  EALLOW; // Allow register-access
177  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << 27); // Enable pull-up on GPIO27 (CAP4)
178  TMC_BASE_PIO->CTL[0].QSEL2 &= ~((Uint32)0x3 << 22); // Synch to SYSCLKOUT GPIO27 (CAP4)
179  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1 << 22); // Configure GPIO27 as CAP4
180  ECAP = TMC_BASE_ECAP4; // Assign Register-address to variable for register access
181  eCAP_configureInterrupt(gpio, &eCAP4_isr, 4); // Configure GPIO27 to call ISR on Capture Event 1
182  EDIS; // Protect register
183  break;
184  }
185  else{
186  return -10; // eCAP4 already in use
187  }
188  case 34: if(!g_ecap1_in_use){
189  g_ecap1_in_use = 1; // Configuring GPIO34 as eCAP1
190  EALLOW; // Allow register-access
191  TMC_BASE_PIO->CTL[1].PUD &= ~(0x1 << 2); // Enable pull-up on GPIO34 (CAP1)
192  TMC_BASE_PIO->CTL[1].QSEL1 &= ~((Uint32)0x3 << 4); //Synch to SYSCLKOUT GPIO34 (CAP1)
193  TMC_BASE_PIO->CTL[1].MUX1 |= ((Uint32)0x1 << 4); // Configure GPIO34 as CAP1
194  ECAP = TMC_BASE_ECAP1; // Assign Register-address to variable for register access
195  eCAP_configureInterrupt(gpio, &eCAP1_isr, 4); // Configure GPIO34 to call ISR on Capture Event 1
196  EDIS; // Protect register
197  break;
198  }
199  else{
200  return -10; // eCAP1 already in use
201  }
202  case 37: if(!g_ecap2_in_use){
203  g_ecap2_in_use=1; // Configuring GPIO37 as eCAP2
204  EALLOW; // Allow register-access
205  TMC_BASE_PIO->CTL[1].PUD &= ~(0x1 << 5); // Enable pull-up on GPIO37 (CAP2)
206  TMC_BASE_PIO->CTL[1].QSEL1 &= ~((Uint32)0x3 << 10); // Synch to SYSCLKOUT GPIO37 (CAP2)
207  TMC_BASE_PIO->CTL[1].MUX1 |= ((Uint32)0x3 << 10); // Configure GPIO37 as CAP2
208  ECAP = TMC_BASE_ECAP2; // Assign Register-address to variable for register access
209  eCAP_configureInterrupt(gpio, &eCAP2_isr, 4); // Configure GPIO37 to call ISR on Capture Event 1
210  EDIS; // Protect register
211  break;
212  }
213  else{
214  return -10; // eCAP2 already in use
215  }
216  case 48: if(!g_ecap5_in_use){
217  g_ecap5_in_use = 1; // Configuring GPIO48 as eCAP5
218  EALLOW; // Allow register-access
219  TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1 << 16); // Enable pull-up on GPIO48 (CAP5)
220  TMC_BASE_PIO->CTL[1].QSEL2 &= ~((Uint32)0x3); // Synch to SYSCLKOUT GPIO48 (CAP5)
221  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1); // Configure GPIO48 as CAP5
222  ECAP = TMC_BASE_ECAP5; // Assign Register-address to variable for register access
223  eCAP_configureInterrupt(gpio, &eCAP5_isr, 4); // Configure GPIO48 to call ISR on Capture Event 1
224  EDIS; // Protect register
225  break;
226  }
227  else{
228  return -10; // eCAP5 already in use
229  }
230  case 49: if(!g_ecap6_in_use){
231  g_ecap6_in_use = 1; // Configuring GPIO49 as eCAP6
232  EALLOW; // Allow register-access
233  TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1 << 17); // Enable pull-up on GPIO49 (CAP6)
234  TMC_BASE_PIO->CTL[1].QSEL2 &= ~((Uint32)0x3 << 2); // Synch to SYSCLKOUT GPIO49 (CAP6)
235  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1 << 2); // Configure GPIO49 as CAP6
236  ECAP = TMC_BASE_ECAP6; // Assign Register-address to variable for register access
237  eCAP_configureInterrupt(gpio, &eCAP6_isr, 4); // Configure GPIO48 to call ISR on Capture Event 1
238  EDIS; // Protect register
239  break;
240  }
241  else{
242  return -10;
243  }
244  default: return -1;
245  }
246  ECAP->ECEINT &= ~(0xFFFF); // Disable all capture interrupts
247  ECAP->ECCLR |= 0xFFFF; // Clear all CAP interrupt flags
248  ECAP->ECCTL1 &= ~(0x1 << 8); // Disable CAP1-CAP4 register loads
249  ECAP->ECCTL2 &= ~(0x1 << 4); // Make sure the counter is stopped
250 
251  // Configure peripheral registers
252  ECAP->ECCTL1 &= ~(0x3E00); // Event Prescaler: bypass
253  ECAP->ECCTL2 |= (0x1); // operate in one-shot mode
254  ECAP->ECCTL2 |= (0x3 << 1); // stop after capture event 4 in one-shot mode
255 
256  ECAP->ECCTL1 &= ~(0x1); // Capture Event 1 triggered on a rising edge (RE)
257  ECAP->ECCTL1 &= ~(0x1 << 2); // Capture Event 2 triggered on a rising edge (RE)
258  ECAP->ECCTL1 &= ~(0x1 << 4); // Capture Event 3 triggered on a rising edge (RE)
259  ECAP->ECCTL1 &= ~(0x1 << 6); // Capture Event 4 triggered on a rising edge (RE)
260 
261  ECAP->ECCTL1 |= (0x1 << 1); // Reset counter after Event 1 time-stamp has been captured
262  ECAP->ECCTL1 |= (0x1 << 3); // Reset counter after Event 2 time-stamp has been captured
263  ECAP->ECCTL1 |= (0x1 << 5); // Reset counter after Event 3 time-stamp has been captured
264  ECAP->ECCTL1 |= (0x1 << 7); // Reset counter after Event 4 time-stamp has been captured
265 
266  ECAP->ECCTL2 &= ~(0x1 << 5); // Disable sync in
267  ECAP->ECCTL2 |= (0x3 << 6); // Disable sync out
268 
269  ECAP->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
270  ECAP->ECCTL2 |= (0x1 << 4); // Start Counter
271  ECAP->ECCTL2 |= (0x1 << 3); // re arm counter
272  ECAP->ECEINT |= (0x1 << 4); // Capture Event 4 Interrupt Enable
273  ECAP->ECEINT |= (0x1 << 5); // Capture Counter overflow Interrupt Enable
274 
275  return 0;
276 }
277 
289 int16 eCAP_configureInterrupt(Uint16 gpio, void * isr, Uint16 event){
290  DINT; // Disable CPU interrupts
291  if(event > 0 && event <= 7){ // check event
292  EALLOW;
293  switch(gpio){
294  case 1: if(g_ecap6_in_use){
295  TMC_BASE_ECAP6->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
296  TMC_BASE_INT_REGS->ECAP6_INT = (Uint32)isr; // assign ISR
297  TMC_BASE_PIE->GROUP[3].IER |= 0x20; // Enable eCAP6 in the PIE: Group 4 interrupt 6
298  break;
299  }
300  else{
301  return -20;
302  }
303  case 3: if(g_ecap5_in_use){
304  TMC_BASE_ECAP5->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
305  TMC_BASE_INT_REGS->ECAP5_INT = (Uint32)isr; // assign ISR
306  TMC_BASE_PIE->GROUP[3].IER |= 0x10; // Enable eCAP5 in the PIE: Group 4 interrupt 5
307  break;
308  }
309  else{
310  return -20;
311  }
312  case 5: if(g_ecap1_in_use){
313  TMC_BASE_ECAP1->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
314  TMC_BASE_INT_REGS->ECAP1_INT = (Uint32)isr; // assign ISR
315  TMC_BASE_PIE->GROUP[3].IER |= 0x1; // Enable eCAP1 in the PIE: Group 4 interrupt 1
316  break;
317  }
318  else{
319  return -20;
320  }
321  case 7: if(g_ecap2_in_use){
322  TMC_BASE_ECAP2->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
323  TMC_BASE_INT_REGS->ECAP2_INT = (Uint32)isr; // assign ISR
324  TMC_BASE_PIE->GROUP[3].IER |= 0x2; // Enable eCAP2 in the PIE: Group 4 interrupt 2
325  break;
326  }
327  else{
328  return -20;
329  }
330  case 9: if(g_ecap3_in_use){
331  TMC_BASE_ECAP3->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
332  TMC_BASE_INT_REGS->ECAP3_INT = (Uint32)isr; // assign ISR
333  TMC_BASE_PIE->GROUP[3].IER |= 0x4; // Enable eCAP3 in the PIE: Group 4 interrupt 3
334  break;
335  }
336  else{
337  return -20;
338  }
339  case 11: if(g_ecap4_in_use){
340  TMC_BASE_ECAP4->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
341  TMC_BASE_INT_REGS->ECAP4_INT = (Uint32)isr; // assign ISR
342  TMC_BASE_PIE->GROUP[3].IER |= 0x8; // Enable eCAP4 in the PIE: Group 4 interrupt 4
343  break;
344  }
345  else{
346  return -20;
347  }
348  case 24: if(g_ecap1_in_use){
349  TMC_BASE_ECAP1->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
350  TMC_BASE_INT_REGS->ECAP1_INT = (Uint32)isr; // assign ISR
351  TMC_BASE_PIE->GROUP[3].IER |= 0x1; // Enable eCAP1 in the PIE: Group 4 interrupt 1
352  break;
353  }
354  else{
355  return -20;
356  }
357  case 25: if(g_ecap2_in_use){
358  TMC_BASE_ECAP2->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
359  TMC_BASE_INT_REGS->ECAP2_INT = (Uint32)isr; // assign ISR
360  TMC_BASE_PIE->GROUP[3].IER |= 0x2; // Enable eCAP2 in the PIE: Group 4 interrupt 2
361  break;
362  }
363  else{
364  return -20;
365  }
366  case 26: if(g_ecap3_in_use){
367  TMC_BASE_ECAP3->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
368  TMC_BASE_INT_REGS->ECAP3_INT = (Uint32)isr; // assign ISR
369  TMC_BASE_PIE->GROUP[3].IER |= 0x4; // Enable eCAP3 in the PIE: Group 4 interrupt 3
370  break;
371  }
372  else{
373  return -20;
374  }
375  case 27: if(g_ecap4_in_use){
376  TMC_BASE_ECAP4->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
377  TMC_BASE_INT_REGS->ECAP4_INT = (Uint32)isr; // assign ISR
378  TMC_BASE_PIE->GROUP[3].IER |= 0x8; // Enable eCAP4 in the PIE: Group 4 interrupt 4
379  break;
380  }
381  else{
382  return -20;
383  }
384  case 34: if(g_ecap1_in_use){
385  TMC_BASE_ECAP1->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
386  TMC_BASE_INT_REGS->ECAP1_INT = (Uint32)isr; // assign ISR
387  TMC_BASE_PIE->GROUP[3].IER |= 0x1; // Enable eCAP1 in the PIE: Group 4 interrupt 1
388  break;
389  }
390  else{
391  return -20;
392  }
393  case 37: if(g_ecap2_in_use){
394  TMC_BASE_ECAP2->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
395  TMC_BASE_INT_REGS->ECAP2_INT = (Uint32)isr; // assign ISR
396  TMC_BASE_PIE->GROUP[3].IER |= 0x2; // Enable eCAP2 in the PIE: Group 4 interrupt 2
397  break;
398  }
399  else{
400  return -20;
401  }
402  case 48: if(g_ecap5_in_use){
403  TMC_BASE_ECAP5->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
404  TMC_BASE_INT_REGS->ECAP5_INT = (Uint32)isr; // assign ISR
405  TMC_BASE_PIE->GROUP[3].IER |= 0x10; // Enable eCAP5 in the PIE: Group 4 interrupt 5
406  break;
407  }
408  else{
409  return -20;
410  }
411  case 49: if(g_ecap6_in_use){
412  TMC_BASE_ECAP6->ECEINT |= (0x1 << event); // Enable eCAP-Interrupt for requested event on requested Pin
413  TMC_BASE_INT_REGS->ECAP6_INT = (Uint32)isr; // assign ISR
414  TMC_BASE_PIE->GROUP[3].IER |= 0x20; // Enable eCAP6 in the PIE: Group 4 interrupt 6
415  break;
416  }
417  else{
418  return -20;
419  }
420  default: EDIS;
421  return -1;
422  }
423  EDIS;
424  }
425  else{
426  return -16;
427  }
428  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
429  IER |= 0x0008; // Enable CPU INT4 which is connected to ECAP1-4 INT
430  EINT; // Enable Global interrupt
431  ERTM; // Enable Global realtime interrupt DBGM
432  return 0;
433 }
434 
446 int16 eCAP_pwmOutput(Uint16 gpio, Uint32 frequency, Uint16 dutycycle){
447  TMPS_ECAP ECAP;
448  if((frequency > 1000000) || (frequency < 1)){
449  return -5;
450  }
451  else if(dutycycle > 100){
452  return -6;
453  }
454  else{
455  switch(gpio){
456  case 1: ECAP = TMC_BASE_ECAP6;
457  break;
458  case 3: ECAP = TMC_BASE_ECAP5;
459  break;
460  case 5: ECAP = TMC_BASE_ECAP1;
461  break;
462  case 7: ECAP = TMC_BASE_ECAP2;
463  break;
464  case 9: ECAP = TMC_BASE_ECAP3;
465  break;
466  case 11: ECAP = TMC_BASE_ECAP4;
467  break;
468  case 24: ECAP = TMC_BASE_ECAP1;
469  break;
470  case 25: ECAP = TMC_BASE_ECAP2;
471  break;
472  case 26: ECAP = TMC_BASE_ECAP3;
473  break;
474  case 27: ECAP = TMC_BASE_ECAP4;
475  break;
476  case 34: ECAP = TMC_BASE_ECAP1;
477  break;
478  case 37: ECAP = TMC_BASE_ECAP2;
479  break;
480  case 48: ECAP = TMC_BASE_ECAP5;
481  break;
482  case 49: ECAP = TMC_BASE_ECAP6;
483  break;
484  default: return -1;
485  }
486  // Setup APWM mode on CAP-Pin, set period and compare registers
487  ECAP->ECCTL2 |= (0x1 << 9); // Enable APWM mode
488  ECAP->CAP1 |= (F_CPU/frequency); // Set Period value
489  ECAP->CAP2 |= (((Uint64)ECAP->CAP1 * dutycycle) / 100); // Set Compare value
490  ECAP->CTRPHS &= ~(0x1); // No phase control synchronization
491  ECAP->ECCTL2 &= ~(0x1 << 10); // Output is active high (Compare value defines high time)
492  ECAP->ECCTL2 &= ~(0x1 << 5); // Disable sync-in option
493  ECAP->ECCTL2 |= (0x1 << 6); // Select CTR = PRD event to be the sync-out signal
494  ECAP->ECCTL2 |= (0x1 << 4); // Start counter
495  }
496  return 0;
497 }
498 
507 int64 eCAP_getFrequency(Uint16 gpio){
508  switch(gpio){
509  case 1: if(g_ecap6_in_use){
510  if(g_time_ecap6 > 0){
511  return (F_CPU/g_time_ecap6);
512  }
513  else{
514  return 0;
515  }
516  }
517  else{
518  return -20;
519  }
520  case 3: if(g_ecap5_in_use){
521  if(g_time_ecap5 > 0){
522  return (F_CPU/g_time_ecap5);
523  }
524  else{
525  return 0;
526  }
527  }
528  else{
529  return -20;
530  }
531  case 5: if(g_ecap1_in_use){
532  if(g_time_ecap1 > 0){
533  return (F_CPU/g_time_ecap1);
534  }
535  else{
536  return 0;
537  }
538  }
539  else{
540  return -20;
541  }
542  case 7: if(g_ecap2_in_use){
543  if(g_time_ecap2 > 0){
544  return (F_CPU/g_time_ecap2);
545  }
546  else{
547  return 0;
548  }
549  }
550  else{
551  return -20;
552  }
553  case 9: if(g_ecap3_in_use){
554  if(g_time_ecap3 > 0){
555  return (F_CPU/g_time_ecap3);
556  }
557  else{
558  return 0;
559  }
560  }
561  else{
562  return -20;
563  }
564  case 11: if(g_ecap4_in_use){
565  if(g_time_ecap4 > 0){
566  return (F_CPU/g_time_ecap4);
567  }
568  else{
569  return 0;
570  }
571  }
572  else{
573  return -20;
574  }
575  case 24: if(g_ecap1_in_use){
576  if(g_time_ecap1 > 0){
577  return (F_CPU/g_time_ecap1);
578  }
579  else{
580  return 0;
581  }
582  }
583  else{
584  return -20;
585  }
586  case 25: if(g_ecap2_in_use){
587  if(g_time_ecap2 > 0){
588  return (F_CPU/g_time_ecap2);
589  }
590  else{
591  return 0;
592  }
593  }
594  else{
595  return -20;
596  }
597  case 26: if(g_ecap3_in_use){
598  if(g_time_ecap3 > 0){
599  return (F_CPU/g_time_ecap3);
600  }
601  else{
602  return 0;
603  }
604  }
605  else{
606  return -20;
607  }
608  case 27: if(g_ecap4_in_use){
609  if(g_time_ecap4 > 0){
610  return (F_CPU/g_time_ecap4);
611  }
612  else{
613  return 0;
614  }
615  }
616  else{
617  return -20;
618  }
619  case 34: if(g_ecap1_in_use){
620  if(g_time_ecap1 > 0){
621  return (F_CPU/g_time_ecap1);
622  }
623  else{
624  return 0;
625  }
626  }
627  else{
628  return -20;
629  }
630  case 37: if(g_ecap2_in_use){
631  if(g_time_ecap2 > 0){
632  return (F_CPU/g_time_ecap2);
633  }
634  else{
635  return 0;
636  }
637  }
638  else{
639  return -20;
640  }
641  case 48: if(g_ecap5_in_use){
642  if(g_time_ecap5 > 0){
643  return (F_CPU/g_time_ecap5);
644  }
645  else{
646  return 0;
647  }
648  }
649  else{
650  return -20;
651  }
652  case 49: if(g_ecap6_in_use){
653  if(g_time_ecap6 > 0){
654  return (F_CPU/g_time_ecap6);
655  }
656  else{
657  return 0;
658  }
659  }
660  else{
661  return -20;
662  }
663  default: return -1;
664  }
665 }
666 
672 __interrupt void eCAP1_isr(void){
673  if((TMC_BASE_ECAP1->ECFLG & 0x0020) && !(TMC_BASE_ECAP1->ECFLG & 0x0010)){ //Timer overflow
674  g_time_ecap1 = 0;
675  TMC_BASE_ECAP1->ECCLR |= (0x1 << 5); // Clear the Overflow flag
676  }
677  else{
678  g_time_ecap1 = TMC_BASE_ECAP1->CAP2; // Get value of time_diff between two rising edges
679  TMC_BASE_ECAP1->ECCLR |= (0x1 << 4); // Clear the CEVT4 flag
680  }
681  TMC_BASE_ECAP1->ECCLR |= 0x1; // Clear global Int Flag
682 
683  TMC_BASE_ECAP1->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
684  TMC_BASE_ECAP1->ECCTL2 |= (0x1 << 4); // Start Counter
685  TMC_BASE_ECAP1->ECCTL2 |= (0x1 << 3); // re arm counter
686  TMC_BASE_PIE->ACK |= 0x8; // Interrupt ACK
687 }
688 
694 __interrupt void eCAP2_isr(void){
695  if((TMC_BASE_ECAP2->ECFLG & 0x0020) && !(TMC_BASE_ECAP2->ECFLG & 0x0010)){ //Timer overflow
696  g_time_ecap2 = 0;
697  TMC_BASE_ECAP2->ECCLR |= (0x1 << 5); // Clear the Overflow flag
698  }
699  else{
700  g_time_ecap2 = TMC_BASE_ECAP2->CAP2; // Get value of time_diff between two rising edges
701  TMC_BASE_ECAP2->ECCLR |= (0x1 << 4); // Clear the CEVT4 flag
702  }
703  TMC_BASE_ECAP2->ECCLR |= 0x1; // Clear global Int Flag
704 
705  TMC_BASE_ECAP2->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
706  TMC_BASE_ECAP2->ECCTL2 |= (0x1 << 4); // Start Counter
707  TMC_BASE_ECAP2->ECCTL2 |= (0x1 << 3); // re arm counter
708  TMC_BASE_PIE->ACK |= 0x8; // Interrupt ACK
709 }
710 
716 __interrupt void eCAP3_isr(void){
717  if((TMC_BASE_ECAP3->ECFLG & 0x0020) && !(TMC_BASE_ECAP3->ECFLG & 0x0010)){ //Timer overflow
718  g_time_ecap3 = 0;
719  TMC_BASE_ECAP3->ECCLR |= (0x1 << 5); // Clear the Overflow flag
720  }
721  else{
722  g_time_ecap3 = TMC_BASE_ECAP3->CAP2; // Get value of time_diff between two rising edges
723  TMC_BASE_ECAP3->ECCLR |= (0x1 << 4); // Clear the CEVT4 flag
724  }
725  TMC_BASE_ECAP3->ECCLR |= 0x1; // Clear global Int Flag
726 
727  TMC_BASE_ECAP3->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
728  TMC_BASE_ECAP3->ECCTL2 |= (0x1 << 4); // Start Counter
729  TMC_BASE_ECAP3->ECCTL2 |= (0x1 << 3); // re arm counter
730  TMC_BASE_PIE->ACK |= 0x8; // Interrupt ACK
731 }
732 
738 __interrupt void eCAP4_isr(void){
739  if((TMC_BASE_ECAP4->ECFLG & 0x0020) && !(TMC_BASE_ECAP4->ECFLG & 0x0010)){ //Timer overflow
740  g_time_ecap4 = 0;
741  TMC_BASE_ECAP4->ECCLR |= (0x1 << 5); // Clear the Overflow flag
742  }
743  else{
744  g_time_ecap4 = TMC_BASE_ECAP4->CAP2; // Get value of time_diff between two rising edges
745  TMC_BASE_ECAP4->ECCLR |= (0x1 << 4); // Clear the CEVT4 flag
746  }
747  TMC_BASE_ECAP4->ECCLR |= 0x1; // Clear global Int Flag
748 
749  TMC_BASE_ECAP4->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
750  TMC_BASE_ECAP4->ECCTL2 |= (0x1 << 4); // Start Counter
751  TMC_BASE_ECAP4->ECCTL2 |= (0x1 << 3); // re arm counter
752  TMC_BASE_PIE->ACK |= 0x8; // Interrupt ACK
753 }
754 
760 __interrupt void eCAP5_isr(void){
761  if((TMC_BASE_ECAP5->ECFLG & 0x0020) && !(TMC_BASE_ECAP5->ECFLG & 0x0010)){ //Timer overflow
762  g_time_ecap5 = 0;
763  TMC_BASE_ECAP5->ECCLR |= (0x1 << 5); // Clear the Overflow flag
764  }
765  else{
766  g_time_ecap5 = TMC_BASE_ECAP5->CAP2; // Get value of time_diff between two rising edges
767  TMC_BASE_ECAP5->ECCLR |= (0x1 << 4); // Clear the CEVT4 flag
768  }
769  TMC_BASE_ECAP5->ECCLR |= 0x1; // Clear global Int Flag
770 
771  TMC_BASE_ECAP5->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
772  TMC_BASE_ECAP5->ECCTL2 |= (0x1 << 4); // Start Counter
773  TMC_BASE_ECAP5->ECCTL2 |= (0x1 << 3); // re arm counter
774  TMC_BASE_PIE->ACK |= 0x8; // Interrupt ACK
775 }
776 
782 __interrupt void eCAP6_isr(void){
783  if((TMC_BASE_ECAP6->ECFLG & 0x0020) && !(TMC_BASE_ECAP6->ECFLG & 0x0010)){ //Timer overflow
784  g_time_ecap6 = 0;
785  TMC_BASE_ECAP6->ECCLR |= (0x1 << 5); // Clear the Overflow flag
786  }
787  else{
788  g_time_ecap6 = TMC_BASE_ECAP6->CAP2; // Get value of time_diff between two rising edges
789  TMC_BASE_ECAP6->ECCLR |= (0x1 << 4); // Clear the CEVT4 flag
790  }
791  TMC_BASE_ECAP6->ECCLR |= 0x1; // Clear global Int Flag
792 
793  TMC_BASE_ECAP6->ECCTL1 |= (0x1 << 8); // Enable Loading of CAP1-4 registers on a capture event
794  TMC_BASE_ECAP6->ECCTL2 |= (0x1 << 4); // Start Counter
795  TMC_BASE_ECAP6->ECCTL2 |= (0x1 << 3); // re arm counter
796  TMC_BASE_PIE->ACK |= 0x8; // Interrupt ACK
797 }
798 
806 int16 eCAP_forceTimerOverflowInterrupt(Uint16 gpio){
807  switch(gpio){
808  case 1: TMC_BASE_ECAP6->ECFRC |= (0x1 << 5);
809  break;
810  case 3: TMC_BASE_ECAP5->ECFRC |= (0x1 << 5);
811  break;
812  case 5: TMC_BASE_ECAP1->ECFRC |= (0x1 << 5);
813  break;
814  case 7: TMC_BASE_ECAP2->ECFRC |= (0x1 << 5);
815  break;
816  case 9: TMC_BASE_ECAP3->ECFRC |= (0x1 << 5);
817  break;
818  case 11: TMC_BASE_ECAP4->ECFRC |= (0x1 << 5);
819  break;
820  case 24: TMC_BASE_ECAP1->ECFRC |= (0x1 << 5);
821  break;
822  case 25: TMC_BASE_ECAP2->ECFRC |= (0x1 << 5);
823  break;
824  case 26: TMC_BASE_ECAP3->ECFRC |= (0x1 << 5);
825  break;
826  case 27: TMC_BASE_ECAP4->ECFRC |= (0x1 << 5);
827  break;
828  case 34: TMC_BASE_ECAP1->ECFRC |= (0x1 << 5);
829  break;
830  case 37: TMC_BASE_ECAP2->ECFRC |= (0x1 << 5);
831  break;
832  case 48: TMC_BASE_ECAP5->ECFRC |= (0x1 << 5);
833  break;
834  case 49: TMC_BASE_ECAP6->ECFRC |= (0x1 << 5);
835  break;
836  default: return -1;
837  }
838  return 0;
839 }
g_time_ecap6
Uint32 g_time_ecap6
Definition: ecap.c:27
_TMS_ECAP::CAP2
TM_REG32 CAP2
Capture 2 Register.
Definition: TMC_BASE_ECAP.h:20
_TMS_ECAP::ECCTL1
TM_REG16 ECCTL1
Capture Control Register 1.
Definition: TMC_BASE_ECAP.h:24
eCAP1_isr
__interrupt void eCAP1_isr(void)
Interrupt Service Routine of eCAP1.
Definition: ecap.c:672
TMC_BASE_PIE.h
PIE-Register header file.
int16
int int16
16 Bit Variable: - 32.768 .. 32.767
Definition: global_defines.h:17
eCAP6_isr
__interrupt void eCAP6_isr(void)
Interrupt Service Routine of eCAP6.
Definition: ecap.c:782
eCAP_forceTimerOverflowInterrupt
int16 eCAP_forceTimerOverflowInterrupt(Uint16 gpio)
Force eCAP Timer overflow for setting frequency to 0.
Definition: ecap.c:806
IER
cregister volatile unsigned int IER
Generate reference to Interrupt Enable Register.
eCAP3_isr
__interrupt void eCAP3_isr(void)
Interrupt Service Routine of eCAP3.
Definition: ecap.c:716
g_time_ecap4
Uint32 g_time_ecap4
Definition: ecap.c:25
ecap.h
Header file for eCAP module.
g_time_ecap3
Uint32 g_time_ecap3
Definition: ecap.c:24
Uint64
unsigned long long Uint64
64 Bit Variable: 0 .. 18.446.744.073.709.551.615
Definition: global_defines.h:23
g_time_ecap5
Uint32 g_time_ecap5
Definition: ecap.c:26
eCAP4_isr
__interrupt void eCAP4_isr(void)
Interrupt Service Routine of eCAP4.
Definition: ecap.c:738
_TMS_ECAP::ECCTL2
TM_REG16 ECCTL2
Capture Control Register 2.
Definition: TMC_BASE_ECAP.h:25
_TMS_ECAP::CTRPHS
TM_REG32 CTRPHS
Counter Phase Offset Value Register.
Definition: TMC_BASE_ECAP.h:18
eCAP5_isr
__interrupt void eCAP5_isr(void)
Interrupt Service Routine of eCAP5.
Definition: ecap.c:760
_TMS_ECAP::ECEINT
TM_REG16 ECEINT
Capture Interrupt Enable Register.
Definition: TMC_BASE_ECAP.h:26
eCAP_pwmOutput
int16 eCAP_pwmOutput(Uint16 gpio, Uint32 frequency, Uint16 dutycycle)
PWM-Output on eCAP-Pin .
Definition: ecap.c:446
init_eCAP
int16 init_eCAP(Uint16 gpio)
Init eCAP-Pin .
Definition: ecap.c:45
global_defines.h
Header file for global defines.
eCAP_getFrequency
int64 eCAP_getFrequency(Uint16 gpio)
Applied frequency on eCAP-Pin .
Definition: ecap.c:507
Uint16
unsigned int Uint16
16 Bit Variable: 0 .. 65.535
Definition: global_defines.h:21
g_time_ecap1
Uint32 g_time_ecap1
Definition: ecap.c:22
eCAP2_isr
__interrupt void eCAP2_isr(void)
Interrupt Service Routine of eCAP2.
Definition: ecap.c:694
TMC_BASE_INT_REGS.h
Interupt-Register header file.
int64
long long int64
64 Bit Variable: - 9.223.372.036.854.775.808 .. 9.223.372.036.854.775.807
Definition: global_defines.h:19
eCAP_configureInterrupt
int16 eCAP_configureInterrupt(Uint16 gpio, void *isr, Uint16 event)
Interrupt on eCAP-Pin .
Definition: ecap.c:289
TMC_BASE_PIO.h
GPIO-Register header file.
_TMS_ECAP
eCAP Register (TMC_BASE_ECAP1 - TMC_BASE_ECAP6).
Definition: TMC_BASE_ECAP.h:16
_TMS_ECAP::ECCLR
TM_REG16 ECCLR
Capture Interrupt Clear Register.
Definition: TMC_BASE_ECAP.h:28
g_time_ecap2
Uint32 g_time_ecap2
Definition: ecap.c:23
TMC_BASE_ECAP.h
eCAP-Register header file
_TMS_ECAP::CAP1
TM_REG32 CAP1
Capture 1 Register.
Definition: TMC_BASE_ECAP.h:19
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22