TMS320F28335 Library  1.0
Documentation
Functions
cpu_timer.h File Reference

Header file for CPU-Timer module. More...

Go to the source code of this file.

Functions

int16 init_CPUTimer (Uint16, void *)
 Init CPU-Timer 0/1/2. More...
 
int16 CPUTimer_start (Uint16, Uint32)
 Start CPU-Timer 0/1/2 || make sure CPU-Timer has been initialized. More...
 
int16 CPUTimer_stop (Uint16)
 Stop CPU-Timer 0/1/2 || make sure CPU-Timer has been initialized. More...
 
void CPUTimer_interruptAck (void)
 Set Acknowledge to receive another interrupt from CPU-Timer. More...
 

Detailed Description

Header file for CPU-Timer module.

Definition in file cpu_timer.h.

Function Documentation

◆ CPUTimer_interruptAck()

void CPUTimer_interruptAck ( void  )

Set Acknowledge to receive another interrupt from CPU-Timer.

Definition at line 171 of file cpu_timer.c.

171  {
172  TMC_BASE_PIE->ACK |= 0x1; // Acknowledge interrupt to get more from group 1
173 }

◆ CPUTimer_start()

int16 CPUTimer_start ( Uint16  cpu_timer,
Uint32  Period 
)

Start CPU-Timer 0/1/2 || make sure CPU-Timer has been initialized.

Parameters
[in]1) CPU-Timer as Uint16 --> valid value: 0-2
2) Period for Timer-Interrupt in microseconds
Returns
Result of operations as int16
--> 0 = operation successful
--> -19 = invalid value of CPU-Timer
--> -20 = requested CPU-Timer not configured

Definition at line 89 of file cpu_timer.c.

89  {
90  Uint32 temp;
91  temp = (long) ((float)150 * Period); //calculate microseconds to frequency
92 
93  switch (cpu_timer){
94  case 0: if(g_cpu_timer_0_in_use){
95  TMC_BASE_TIMER0->PRD = (Uint16)(temp&0xFFFF); // Set Period Low for Timer
96  TMC_BASE_TIMER0->PRDH = (Uint16)(temp >> 16); // Set Period High for Timer
97  TMC_BASE_TIMER0->TPR = 0; // Disable Prescaler
98  TMC_BASE_TIMER0->TPRH = 0; // Disable Prescaler
99  TMC_BASE_TIMER0->TCR |= (0x1 << 4); // Stop timer
100  TMC_BASE_TIMER0->TCR |= (0x1 << 5); // reload timer
101  TMC_BASE_TIMER0->TCR |= (0x2 << 10); // Run in Free mode
102  TMC_BASE_TIMER0->TCR |= ((Uint32)0x1 << 14); // Enable Timer Interrupt
103  TMC_BASE_TIMER0->TCR &= ~(0x1 << 4); // Start/Restart Timer
104  break;
105  }
106  else{
107  return -20;
108  }
109 
110  case 1: if(g_cpu_timer_1_in_use){
111  TMC_BASE_TIMER1->PRD = (Uint16)(temp&0xFFFF); // Set Period Low for Timer
112  TMC_BASE_TIMER1->PRDH = (Uint16)(temp >> 16); // Set Period High for Timer
113  TMC_BASE_TIMER1->TPR = 0; // Disable Prescaler
114  TMC_BASE_TIMER1->TPRH = 0; // Disable Prescaler
115  TMC_BASE_TIMER1->TCR |= (0x1 << 4); // Stop timer
116  TMC_BASE_TIMER1->TCR |= (0x1 << 5); // Reload timer
117  TMC_BASE_TIMER1->TCR |= (0x2 << 10); // Run in Free mode
118  TMC_BASE_TIMER1->TCR |= ((Uint32)0x1 << 14); // Enable Timer Interrupt
119  TMC_BASE_TIMER1->TCR &= ~(0x1 << 4); // Start/Restart Timer
120  break;
121  }
122  else{
123  return -20;
124  }
125  case 2: if(g_cpu_timer_2_in_use){
126  TMC_BASE_TIMER2->PRD = (Uint16)(temp&0xFFFF); // Set Period Low for Timer
127  TMC_BASE_TIMER2->PRDH = (Uint16)(temp >> 16); // Set Period High for Timer
128  TMC_BASE_TIMER2->TPR = 0; // Disable Prescaler
129  TMC_BASE_TIMER2->TPRH = 0; // Disable Prescaler
130  TMC_BASE_TIMER2->TCR |= (0x1 << 4); // Stop timer
131  TMC_BASE_TIMER2->TCR |= (0x1 << 5); // reload timer
132  TMC_BASE_TIMER2->TCR |= (0x2 << 10); // Run in Free mode
133  TMC_BASE_TIMER2->TCR |= ((Uint32)0x1 << 14); // Enable Timer Interrupt
134  TMC_BASE_TIMER2->TCR &= ~(0x1 << 4); // Start/Restart Timer
135  break;
136  }
137  else{
138  return -20;
139  }
140  default: return -19;
141  }
142  return 0;
143 }

◆ CPUTimer_stop()

int16 CPUTimer_stop ( Uint16  cpu_timer)

Stop CPU-Timer 0/1/2 || make sure CPU-Timer has been initialized.

Parameters
[in]1) CPU-Timer as Uint16 --> valid value: 0-2
Returns
Result of operations as int16
--> 0 = operation successful
--> -19 = invalid value of CPU-Timer

Definition at line 152 of file cpu_timer.c.

152  {
153  switch (cpu_timer){
154  case 0: TMC_BASE_TIMER0->TCR &= ~((Uint32)0x1 << 14); // Disable Interrupt
155  TMC_BASE_TIMER0->TCR |= (0x1 << 4); // Stop timer
156  break;
157  case 1: TMC_BASE_TIMER1->TCR &= ~((Uint32)0x1 << 14); // Disable Interrupt
158  TMC_BASE_TIMER1->TCR |= (0x1 << 4); // Stop timer
159  break;
160  case 2: TMC_BASE_TIMER2->TCR &= ~((Uint32)0x1 << 14); // Disable Interrupt
161  TMC_BASE_TIMER2->TCR |= (0x1 << 4); // Stop timer
162  break;
163  default: return -19;
164  }
165  return 0;
166 }

◆ init_CPUTimer()

int16 init_CPUTimer ( Uint16  cpu_timer,
void *  isr 
)

Init CPU-Timer 0/1/2.

Parameters
[in]1) CPU-Timer as Uint16 --> valid value: 0-2
2) Interrupt Service routine
Returns
Result of operations as int16
--> 0 = operation successful
--> -19 = invalid value of CPU-Timer
--> -10 = CPU-Timer already in use

Definition at line 27 of file cpu_timer.c.

27  {
28  switch (cpu_timer){
29  case 0: if(!g_cpu_timer_0_in_use){
30  g_cpu_timer_0_in_use=1; // Set flag for in_use
31  DINT; // Disable Interrupts
32  EALLOW; // Allow Register writes
33  TMC_BASE_INT_REGS->CPU_TIMER0 = (Uint32)isr; // Assign Interrupt Service Routine
34  EDIS; // Protect registers
35  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
36  TMC_BASE_PIE->GROUP[0].IER |= 0x40; // Enable TINT0 in the PIE: Group 1 interrupt 7
37  IER |= 0x0001; // Enable CPU int1 which is connected to CPU-Timer 0
38  EINT; // Enable Interrupts
39  TMC_BASE_TIMER0->TCR = (0x1 << 4); // Timer is stopped
40  }
41  else{
42  return -10;
43  }
44  break;
45  case 1: if(!g_cpu_timer_1_in_use){
46  g_cpu_timer_1_in_use=1; // Set flag for in_use
47  DINT; // Disable Interrupts
48  EALLOW; // Allow Register writes
49  TMC_BASE_INT_REGS2->CPU_TIMER1 = (Uint32)isr; // Assign Interrupt Service Routine
50  EDIS; // Protect registers
51  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
52  IER |= 0x1000; // Enable CPU int13 which is connected to CPU-Timer 1
53  EINT; // Enable Interrupts
54  TMC_BASE_TIMER1->TCR = (0x1 << 4); // Make sure timer is stopped
55  }
56  else{
57  return -10;
58  }
59  break;
60  case 2: if(!g_cpu_timer_2_in_use){
61  g_cpu_timer_2_in_use=1; // Set flag for in_use
62  DINT; // Disable Interrupts
63  EALLOW; // Allow Register writes
64  TMC_BASE_INT_REGS2->CPU_TIMER2 = (Uint32)isr; // Assign Interrupt Service Routine
65  EDIS; // Protect registers
66  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
67  IER |= 0x2000; // Enable CPU int14 which is connected to CPU-Timer 2
68  EINT; // Enable Interrupts
69  TMC_BASE_TIMER2->TCR = (0x1 << 4); // Make sure timer is stopped
70  }
71  else{
72  return -10;
73  }
74  break;
75  default: return -1;
76  }
77  return 0;
78 }
IER
cregister volatile unsigned int IER
Generate reference to Interrupt Enable Register.
Uint16
unsigned int Uint16
16 Bit Variable: 0 .. 65.535
Definition: global_defines.h:21
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22