_TMS_SCR Struct Reference

PLL, Clocking, Watchdog, and Low-Power Mode Registers (TMC_BASE_SCR). More...

#include <TMC_BASE_SCR.h>

Data Fields
TM_REG16	PLLSTS
	PLL Status Register. More...
TM_REG16	Reserved0 [8]
TM_REG16	HISPCP
	High-Speed Peripheral Clock Prescaler. More...
TM_REG16	LOSPCP
	Low-Speed Peripheral Clock Prescaler Register. More...
TM_REG16	PCLKCR0
	Peripheral Clock Control Register 0. More...
TM_REG16	PCLKCR1
	Peripheral Clock Control Register 1. More...
TM_REG16	LPMCR0
	Low Power Mode Control 0 Register. More...
TM_REG16	Reserved1 [1]
TM_REG16	PCLKCR3
	Peripheral Clock Control Register 3. More...
TM_REG16	PLLCR
	PLL Control Register. More...
TM_REG16	SCSR
	System Control and Status Register. More...
TM_REG16	WDCNTR
	Watchdog Counter Register. More...
TM_REG16	Reserved2 [1]
TM_REG16	WDKEY
	Watchdog Reset Key Register. More...
TM_REG16	Reserved3 [3]
TM_REG16	WDCR
	Watchdog Control Register. More...
TM_REG16	Reserved4 [4]
TM_REG16	MAPCNF
	Use to re-map ePWM/HRPWM to Peripheral Frame 3 where they can be accessed by the DMA (EALLOW protected) More...

Detailed Description

PLL, Clocking, Watchdog, and Low-Power Mode Registers (TMC_BASE_SCR).

Start at address 0x7011
See Technical_Reference_Manual

Definition at line 14 of file TMC_BASE_SCR.h.

Field Documentation

HISPCP

TM_REG16 HISPCP

High-Speed Peripheral Clock Prescaler.

Definition at line 17 of file TMC_BASE_SCR.h.

LOSPCP

TM_REG16 LOSPCP

Low-Speed Peripheral Clock Prescaler Register.

Definition at line 18 of file TMC_BASE_SCR.h.

LPMCR0

TM_REG16 LPMCR0

Low Power Mode Control 0 Register.

Definition at line 21 of file TMC_BASE_SCR.h.

MAPCNF

TM_REG16 MAPCNF

Use to re-map ePWM/HRPWM to Peripheral Frame 3 where they can be accessed by the DMA (EALLOW protected)

Definition at line 32 of file TMC_BASE_SCR.h.

PCLKCR0

TM_REG16 PCLKCR0

Peripheral Clock Control Register 0.

Definition at line 19 of file TMC_BASE_SCR.h.

PCLKCR1

TM_REG16 PCLKCR1

Peripheral Clock Control Register 1.

Definition at line 20 of file TMC_BASE_SCR.h.

PCLKCR3

TM_REG16 PCLKCR3

Peripheral Clock Control Register 3.

Definition at line 23 of file TMC_BASE_SCR.h.

PLLCR

TM_REG16 PLLCR

PLL Control Register.

Definition at line 24 of file TMC_BASE_SCR.h.

PLLSTS

TM_REG16 PLLSTS

PLL Status Register.

Definition at line 15 of file TMC_BASE_SCR.h.

Reserved0

TM_REG16 Reserved0[8]

Definition at line 16 of file TMC_BASE_SCR.h.

Reserved1

TM_REG16 Reserved1[1]

Definition at line 22 of file TMC_BASE_SCR.h.

Reserved2

TM_REG16 Reserved2[1]

Definition at line 27 of file TMC_BASE_SCR.h.

Reserved3

TM_REG16 Reserved3[3]

Definition at line 29 of file TMC_BASE_SCR.h.

Reserved4

TM_REG16 Reserved4[4]

Definition at line 31 of file TMC_BASE_SCR.h.

SCSR

TM_REG16 SCSR

System Control and Status Register.

Definition at line 25 of file TMC_BASE_SCR.h.

WDCNTR

TM_REG16 WDCNTR

Watchdog Counter Register.

Definition at line 26 of file TMC_BASE_SCR.h.

WDCR

TM_REG16 WDCR

Watchdog Control Register.

Definition at line 30 of file TMC_BASE_SCR.h.

WDKEY

TM_REG16 WDKEY

Watchdog Reset Key Register.

Definition at line 28 of file TMC_BASE_SCR.h.