TMS320F28335 Library  1.0
Documentation
spi.c
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1 
5 #include <register/TMC_BASE_INT_REGS.h>
6 #include <register/TMC_BASE_PIE.h>
7 #include <register/TMC_BASE_PIO.h>
8 #include <register/TMC_BASE_SPI.h>
9 #include "spi.h"
10 
22 int16 init_SPIMasterMode(SPIInterface SPI_Int, Uint32 baudrate){
23  EALLOW;
24  switch(SPI_Int.spi_simo){
25  case 16: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<16); // Enable pull-up on GPIO16 (SPISIMOA)
26  TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3); // Asynch input GPIO16 (SPISIMOA)
27  TMC_BASE_PIO->CTL[0].MUX2 |= (0x1); // Configure GPIO16 as SPISIMOA
28 
29  switch(SPI_Int.spi_somi){
30  case 17: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<17); // Enable pull-up on GPIO17 (SPISOMIA)
31  TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3<<2); // Asynch input GPIO17 (SPISOMIA)
32  TMC_BASE_PIO->CTL[0].MUX2 |= (0x1<<2); // Configure GPIO17 as SPISOMIA
33  break;
34  default: EDIS;
35  return -2;
36  }
37  switch(SPI_Int.spi_clk){
38  case 18: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<18); // Enable pull-up on GPIO18 (SPICLKA)
39  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<4); // Asynch input GPIO18 (SPICLKA)
40  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1<<4); // Configure GPIO18 as SPICLKA
41  break;
42  default: EDIS;
43  return -3;
44  }
45  switch(SPI_Int.spi_ss){
46  case 19: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<19); // Enable pull-up on GPIO19 (SPISTEA)
47  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<6); // Asynch input GPIO19 (SPISTEA)
48  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1<<6); // Configure GPIO19 as SPISTEA
49  break;
50  default: EDIS;
51  return -4;
52  }
53  break;
54  case 54: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<22); // Enable pull-up on GPIO54 (SPISIMOA)
55  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<12); // Asynch input GPIO54 (SPISIMOA)
56  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<12); // Configure GPIO54 as SPISIMOA
57 
58  switch(SPI_Int.spi_somi){
59  case 55: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<23); // Enable pull-up on GPIO55 (SPISOMIA)
60  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<14); // Asynch input GPIO55 (SPISOMIA)
61  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<14); // Configure GPIO55 as SPISOMIA
62  break;
63  default: EDIS;
64  return -2;
65  }
66  switch(SPI_Int.spi_clk){
67  case 56: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<24); // Enable pull-up on GPIO56 (SPICLKA)
68  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<16); // Asynch input GPIO56 (SPICLKA)
69  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<16); // Configure GPIO56 as SPICLKA
70  break;
71  default: EDIS;
72  return -3;
73  }
74  switch(SPI_Int.spi_ss){
75  case 57: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<25); // Enable pull-up on GPIO57 (SPISTEA)
76  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<18); // Asynch input GPIO57 (SPISTEA)
77  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<18); // Configure GPIO57 as SPISTEA
78  break;
79  default: EDIS;
80  return -4;
81  }
82  break;
83  default: EDIS;
84  return -1;
85  }
86  EDIS;
87 
88  TMC_BASE_SPIA->CCR &= ~(0x1<<7); // Set in Reset
89 
90  TMC_BASE_SPIA->CTL |= 0x0004; // Enable master mode
91  TMC_BASE_SPIA->CTL |= 0x0002; // Enable transmission
92  TMC_BASE_SPIA->CTL |= 0x0001; // Enable interrupts
93  TMC_BASE_SPIA->BRR |= (F_LSPCLK/baudrate)-1; // Set Baudrate
94  TMC_BASE_SPIA->CCR |= SPI_Int.wordlength_in_bit-1; // Set Wordlength
95 
96  // Initialize SPI FIFO registers
97  TMC_BASE_SPIA->FFRX &= ~(0x1F);
98  TMC_BASE_SPIA->FFRX |= (0x1); // Receive FIFO interrupt when there are 1 or more words in receive fifo
99  TMC_BASE_SPIA->FFRX |= (0x1 << 5); // Enable interrupt
100  TMC_BASE_SPIA->FFRX |= (0x1 << 6); // Clear Interrupt Flag
101  TMC_BASE_SPIA->FFRX |= (0x1 << 13); // Re-enable receive FIFO operation
102 
103  TMC_BASE_SPIA->FFTX &= ~(0x1F); // Transmit FIFO interrupt when Transmit Fifo empty
104  TMC_BASE_SPIA->FFTX |= (0x1 << 5); // Enable Interrupt
105  TMC_BASE_SPIA->FFTX |= (0x1 << 6); // Clear Interrupt Flag
106  TMC_BASE_SPIA->FFTX |= (0x1 << 13); // Release FIFO from reset
107  TMC_BASE_SPIA->FFTX |= (0x1 << 14); // FIFO enhancements enabled
108  TMC_BASE_SPIA->FFTX |= ((Uint32)0x1 << 15); // SPI FIFO resume
109 
110  TMC_BASE_SPIA->FFCT |= (0x8); // Transmit Delay
111  TMC_BASE_SPIA->CCR |= (0x1<<7); // Relinquish SPI from Reset
112 
113  return 0;
114 }
115 
127 int16 init_SPISlaveMode(SPIInterface SPI_Int){
128  EALLOW;
129  switch(SPI_Int.spi_simo){
130  case 16: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<16); // Enable pull-up on GPIO16 (SPISIMOA)
131  TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3); // Asynch input GPIO16 (SPISIMOA)
132  TMC_BASE_PIO->CTL[0].MUX2 |= (0x1); // Configure GPIO16 as SPISIMOA
133 
134  switch(SPI_Int.spi_somi){
135  case 17: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<17); // Enable pull-up on GPIO17 (SPISOMIA)
136  TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3<<2); // Asynch input GPIO17 (SPISOMIA)
137  TMC_BASE_PIO->CTL[0].MUX2 |= (0x1<<2); // Configure GPIO17 as SPISOMIA
138  break;
139  default: EDIS;
140  return -2;
141  }
142  switch(SPI_Int.spi_clk){
143  case 18: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<18); // Enable pull-up on GPIO18 (SPICLKA)
144  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<4); // Asynch input GPIO18 (SPICLKA)
145  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1<<4); // Configure GPIO18 as SPICLKA
146  break;
147  default: EDIS;
148  return -3;
149  }
150  switch(SPI_Int.spi_ss){
151  case 19: TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1<<19); // Enable pull-up on GPIO19 (SPISTEA)
152  TMC_BASE_PIO->CTL[0].QSEL2 |= ((Uint32)0x3<<6); // Asynch input GPIO19 (SPISTEA)
153  TMC_BASE_PIO->CTL[0].MUX2 |= ((Uint32)0x1<<6); // Configure GPIO19 as SPISTEA
154  break;
155  default: EDIS;
156  return -4;
157  }
158  break;
159  case 54: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<22); // Enable pull-up on GPIO54 (SPISIMOA)
160  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<12); // Asynch input GPIO54 (SPISIMOA)
161  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<12); // Configure GPIO54 as SPISIMOA
162 
163  switch(SPI_Int.spi_somi){
164  case 55: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<23); // Enable pull-up on GPIO55 (SPISOMIA)
165  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<14); // Asynch input GPIO55 (SPISOMIA)
166  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<14); // Configure GPIO55 as SPISOMIA
167  break;
168  default: EDIS;
169  return -2;
170  }
171  switch(SPI_Int.spi_clk){
172  case 56: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<24); // Enable pull-up on GPIO56 (SPICLKA)
173  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<16); // Asynch input GPIO56 (SPICLKA)
174  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<16); // Configure GPIO56 as SPICLKA
175  break;
176  default: EDIS;
177  return -3;
178  }
179  switch(SPI_Int.spi_ss){
180  case 57: TMC_BASE_PIO->CTL[1].PUD &= ~((Uint32)0x1<<25); // Enable pull-up on GPIO57 (SPISTEA)
181  TMC_BASE_PIO->CTL[1].QSEL2 |= ((Uint32)0x3<<18); // Asynch input GPIO57 (SPISTEA)
182  TMC_BASE_PIO->CTL[1].MUX2 |= ((Uint32)0x1<<18); // Configure GPIO57 as SPISTEA
183  break;
184  default: EDIS;
185  return -4;
186  }
187  break;
188  default: EDIS;
189  return -1;
190  }
191  EDIS;
192 
193 
194  TMC_BASE_SPIA->CCR &= ~(0x1<<7); // Set in Reset
195 
196  TMC_BASE_SPIA->CTL &= ~(0x0004); // Disable master mode
197  TMC_BASE_SPIA->CTL |= (0x2); // Enable transmission
198  TMC_BASE_SPIA->CTL |= (0x1); // Enable interrupts
199  TMC_BASE_SPIA->CCR |= SPI_Int.wordlength_in_bit-1; // Set Wordlength
200 
201  // Initialize SPI FIFO registers
202  TMC_BASE_SPIA->FFRX |= (0x1<<13); // Re-enable receive FIFO operation
203  TMC_BASE_SPIA->FFRX &= ~(0x1F); // Receive
204  TMC_BASE_SPIA->FFRX |= (0x1); // Set RX FIFO level to 1
205  TMC_BASE_SPIA->FFRX |= (0x1<<5); // Enable interrupt
206  TMC_BASE_SPIA->FFRX |= (0x1<<6); // Clear Interrupt Flag
207 
208 
209  TMC_BASE_SPIA->FFTX |= (0x1<<13); // Release FIFO from reset
210  TMC_BASE_SPIA->FFTX |= (0x1<<14); // FIFO enhancements enabled
211  TMC_BASE_SPIA->FFTX &= ~(0x1F); // Set TX FIFO level to 0
212  TMC_BASE_SPIA->FFTX |= (0x1<<5); // Enable Interrupt
213  TMC_BASE_SPIA->FFTX |= (0x1<<6); // Clear Interrupt Flag
214  TMC_BASE_SPIA->FFTX |= ((Uint32)0x1<<15); // SPI FIFO resume
215 
216  TMC_BASE_SPIA->CCR |= (0x1<<7); // Relinquish SPI from Reset
217 
218  return 0;
219 }
220 
226 void SPI_setTxInterrupt(void * spiTxFIFOISR){
227  DINT; // Disable Interrupts
228  EALLOW; // Allow Register writes
229  TMC_BASE_INT_REGS->SPITXINTA = (Uint32)spiTxFIFOISR; // Assign Interrupt Service Routine
230  EDIS; // Protect registers
231  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
232  TMC_BASE_PIE->GROUP[5].IER |= 0x2; // Enable I2cInt1A in the PIE: Group 6 interrupt 2
233  IER |= 0x0020; // Enable CPU int block
234  EINT; // Enable Interrupts
235 }
236 
242 void SPI_setRxInterrupt(void * spiRxFIFOISR){
243  DINT; // Disable Interrupts
244  EALLOW; // Allow Register writes
245  TMC_BASE_INT_REGS->SPIRXINTA = (Uint32)spiRxFIFOISR; // Assign Interrupt Service Routine
246  EDIS; // Protect registers
247  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
248  TMC_BASE_PIE->GROUP[5].IER |= 0x1; // Enable I2cInt1A in the PIE: Group 6 interrupt 1
249  IER |= 0x0020; // Enable CPU int block
250  EINT; // Enable Interrupts
251 }
252 
258 void SPI_send(Uint16 sdata){
259  if(!(TMC_BASE_SPIA->FFTX & 0x1F00)){ // If Transmit FIFO empty
260  TMC_BASE_SPIA->TXBUF=sdata; // Send data
261  }
262 }
263 
269 void SPI_read(Uint16 *rdata) {
270  if((TMC_BASE_SPIA->FFRX & 0x1F00)){ // If Receive-FIFO not empty
271  *rdata=TMC_BASE_SPIA->RXBUF; // Read data
272  }
273 }
274 
280 void SPI_interruptAck(){
281  TMC_BASE_PIE->ACK |= 0x20; // Acknowledge interrupt to get more from group all interrupt groups
282 }
283 
289 void SPI_clearRxInterruptFlag(void){
290  TMC_BASE_SPIA->FFRX |= (0x1 << 6); // Clear Interrupt Flag
291 }
292 
298 void SPI_clearTxInterruptFlag(){
299  TMC_BASE_SPIA->FFTX |= (0x1 << 6); // Clear Interrupt Flag
300 }
SPI_setTxInterrupt
void SPI_setTxInterrupt(void *spiTxFIFOISR)
Configuration of SPI Tx ISR.
Definition: spi.c:226
TMC_BASE_SPI.h
SPI-Register header file.
TMC_BASE_PIE.h
PIE-Register header file.
int16
int int16
16 Bit Variable: - 32.768 .. 32.767
Definition: global_defines.h:17
IER
cregister volatile unsigned int IER
Generate reference to Interrupt Enable Register.
spi.h
Header file for SPI module.
init_SPISlaveMode
int16 init_SPISlaveMode(SPIInterface SPI_Int)
Initialization of SPI Interface for slave mode.
Definition: spi.c:127
SPI_clearRxInterruptFlag
void SPI_clearRxInterruptFlag(void)
Clear Interrupt Flag for receive operation.
Definition: spi.c:289
_SPIInterface::spi_somi
Uint16 spi_somi
SPI-SOMI-GPIO (GPIO17)
Definition: spi.h:14
SPI_send
void SPI_send(Uint16 sdata)
Send data via SPI.
Definition: spi.c:258
init_SPIMasterMode
int16 init_SPIMasterMode(SPIInterface SPI_Int, Uint32 baudrate)
Initialization of SPI Interface for Master mode.
Definition: spi.c:22
_SPIInterface::spi_simo
Uint16 spi_simo
SPI-SIMO-GPIO (GPIO16)
Definition: spi.h:13
_SPIInterface::wordlength_in_bit
Uint16 wordlength_in_bit
Amount of Databits to be transmitted per SPI-Tx- and Rx-Operation.
Definition: spi.h:17
_SPIInterface::spi_clk
Uint16 spi_clk
SPI-CLOCK-GPIO (GPIO18)
Definition: spi.h:15
SPI_setRxInterrupt
void SPI_setRxInterrupt(void *spiRxFIFOISR)
Configuration of SPI Rx ISR.
Definition: spi.c:242
Uint16
unsigned int Uint16
16 Bit Variable: 0 .. 65.535
Definition: global_defines.h:21
SPI_clearTxInterruptFlag
void SPI_clearTxInterruptFlag()
Clear Interrupt Flag for transmit operation.
Definition: spi.c:298
TMC_BASE_INT_REGS.h
Interupt-Register header file.
SPI_read
void SPI_read(Uint16 *rdata)
Read Rx-data of SPI module.
Definition: spi.c:269
_SPIInterface
SPI Interface: Assign GPIOs to SPI module.
Definition: spi.h:12
TMC_BASE_PIO.h
GPIO-Register header file.
SPI_interruptAck
void SPI_interruptAck()
Giving interrupts acknowledge to interrupt again.
Definition: spi.c:280
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22
_SPIInterface::spi_ss
Uint16 spi_ss
SPI-SlaveSelect-GPIO (GPIO19)
Definition: spi.h:16