TMS320F28335 Library  1.0
Documentation
Functions
epwm.h File Reference

Header file for ePWM module. More...

Go to the source code of this file.

Functions

int16 init_ePWM (Uint16, Uint32)
 Configuration of GPIO as epwm. More...
 
int16 ePWM_start (Uint16, Uint16)
 Start ePWM signal on pin. More...
 
int16 ePWM_stop (Uint16)
 Stop ePWM signal on pin. More...
 

Detailed Description

Header file for ePWM module.

Definition in file epwm.h.

Function Documentation

◆ ePWM_start()

int16 ePWM_start ( Uint16  gpio,
Uint16  dutycycle 
)

Start ePWM signal on pin.

Parameters
[in]1) ePWM pin as Uint16 --> valid value: 0-11
Returns
Result of operations as int16
--> 0 = operation successful
--> -1 = invalid value of GPIO pin --> -6 = invalid value of dutycycle

Definition at line 80 of file epwm.c.

80  {
81  if(dutycycle>100){
82  return -6;
83  }
84  switch(gpio){
85  case 0: TMC_BASE_EPWM1->AQCSFRC &= ~(0x1); // Software forcing is disabled and has no effect
86  TMC_BASE_EPWM1->CMPA = (Uint16) (((Uint32)TMC_BASE_EPWM1->TBPRD * (100-dutycycle)) / 100); // Set compare value
87  break;
88  case 1: TMC_BASE_EPWM1->AQCSFRC &= ~(0x1 << 2); // Software forcing is disabled and has no effect
89  TMC_BASE_EPWM1->CMPB = (Uint16) (((Uint32)TMC_BASE_EPWM1->TBPRD * (100-dutycycle)) / 100); // Set compare value
90  break;
91  case 2: TMC_BASE_EPWM2->AQCSFRC &= ~(0x1); // Software forcing is disabled and has no effect
92  TMC_BASE_EPWM2->CMPA = (Uint16) (((Uint32)TMC_BASE_EPWM2->TBPRD * (100-dutycycle)) / 100); // Set compare value
93  break;
94  case 3: TMC_BASE_EPWM2->AQCSFRC &= ~(0x1 << 2); // Software forcing is disabled and has no effect
95  TMC_BASE_EPWM2->CMPB = (Uint16) (((Uint32)TMC_BASE_EPWM2->TBPRD * (100-dutycycle)) / 100); // Set compare value
96  break;
97  case 4: TMC_BASE_EPWM3->AQCSFRC &= ~(0x1); // Software forcing is disabled and has no effect
98  TMC_BASE_EPWM3->CMPA = (Uint16) (((Uint32)TMC_BASE_EPWM3->TBPRD * (100-dutycycle)) / 100); // Set compare value
99  break;
100  case 5: TMC_BASE_EPWM3->AQCSFRC &= ~(0x1 << 2); // Software forcing is disabled and has no effect
101  TMC_BASE_EPWM3->CMPB = (Uint16) (((Uint32)TMC_BASE_EPWM3->TBPRD * (100-dutycycle)) / 100); // Set compare value
102  break;
103  case 6: TMC_BASE_EPWM4->AQCSFRC &= ~(0x1); // Software forcing is disabled and has no effect
104  TMC_BASE_EPWM4->CMPA = (Uint16) (((Uint32)TMC_BASE_EPWM4->TBPRD * (100-dutycycle)) / 100); // Set compare value
105  break;
106  case 7: TMC_BASE_EPWM4->AQCSFRC &= ~(0x1 << 2); // Software forcing is disabled and has no effect
107  TMC_BASE_EPWM4->CMPB = (Uint16) (((Uint32)TMC_BASE_EPWM4->TBPRD * (100-dutycycle)) / 100); // Set compare value
108  break;
109  case 8: TMC_BASE_EPWM5->AQCSFRC &= ~(0x1); // Software forcing is disabled and has no effect
110  TMC_BASE_EPWM5->CMPA =(Uint16) (((Uint32)TMC_BASE_EPWM5->TBPRD * (100-dutycycle)) / 100); // Set compare value
111  break;
112  case 9: TMC_BASE_EPWM5->AQCSFRC &= ~(0x1 << 2); // Software forcing is disabled and has no effect
113  TMC_BASE_EPWM5->CMPB = (Uint16) (((Uint32)TMC_BASE_EPWM5->TBPRD * (100-dutycycle)) / 100); // Set compare value
114  break;
115  case 10: TMC_BASE_EPWM6->AQCSFRC &= ~(0x1); // Software forcing is disabled and has no effect
116  TMC_BASE_EPWM6->CMPA = (Uint16) (((Uint32)TMC_BASE_EPWM6->TBPRD * (100-dutycycle)) / 100); // Set compare value
117  break;
118  case 11: TMC_BASE_EPWM6->AQCSFRC &= ~(0x1 << 2); // Software forcing is disabled and has no effect
119  TMC_BASE_EPWM6->CMPB = (Uint16) (((Uint32)TMC_BASE_EPWM6->TBPRD * (100-dutycycle)) / 100); // Set compare value
120  break;
121  default: return -1;
122  }
123  return 0;
124 }

◆ ePWM_stop()

int16 ePWM_stop ( Uint16  gpio)

Stop ePWM signal on pin.

Parameters
[in]1) ePWM pin as Uint16 --> valid value: 0-11
Returns
Result of operations as int16
--> 0 = operation successful
--> -1 = invalid value of GPIO pin

Definition at line 133 of file epwm.c.

133  {
134  switch(gpio){
135  case 0: TMC_BASE_EPWM1->CMPA = TMC_BASE_EPWM1->TBPRD; // Set CMPA = TBPRD
136  TMC_BASE_EPWM1->AQCSFRC |= 0x1; // Forces a continuous low on output A
137  break;
138  case 1: TMC_BASE_EPWM1->CMPB = TMC_BASE_EPWM1->TBPRD; // Set CMPB = TBPRD
139  TMC_BASE_EPWM1->AQCSFRC |= (0x1<<2); // Forces a continuous low on output B
140  break;
141  case 2: TMC_BASE_EPWM2->CMPA = TMC_BASE_EPWM2->TBPRD; // Set CMPA = TBPRD
142  TMC_BASE_EPWM2->AQCSFRC |= 0x1; // Forces a continuous low on output A
143  break;
144  case 3: TMC_BASE_EPWM2->CMPB = TMC_BASE_EPWM2->TBPRD; // Set CMPB = TBPRD
145  TMC_BASE_EPWM2->AQCSFRC |= (0x1<<2); // Forces a continuous low on output B
146  break;
147  case 4: TMC_BASE_EPWM3->CMPA = TMC_BASE_EPWM3->TBPRD; // Set CMPA = TBPRD
148  TMC_BASE_EPWM3->AQCSFRC |= 0x1; // Forces a continuous low on output A
149  break;
150  case 5: TMC_BASE_EPWM3->CMPB = TMC_BASE_EPWM3->TBPRD; // Set CMPB = TBPRD
151  TMC_BASE_EPWM3->AQCSFRC |= (0x1<<2); // Forces a continuous low on output B
152  break;
153  case 6: TMC_BASE_EPWM4->CMPA = TMC_BASE_EPWM4->TBPRD; // Set CMPA = TBPRD
154  TMC_BASE_EPWM4->AQCSFRC |= 0x1; // Forces a continuous low on output A
155  break;
156  case 7: TMC_BASE_EPWM4->CMPB = TMC_BASE_EPWM4->TBPRD; // Set CMPB = TBPRD
157  TMC_BASE_EPWM4->AQCSFRC |= (0x1<<2); // Forces a continuous low on output B
158  break;
159  case 8: TMC_BASE_EPWM5->CMPA = TMC_BASE_EPWM5->TBPRD; // Set CMPA = TBPRD
160  TMC_BASE_EPWM5->AQCSFRC |= 0x1; // Forces a continuous low on output A
161  break;
162  case 9: TMC_BASE_EPWM5->CMPB = TMC_BASE_EPWM5->TBPRD; // Set CMPB = TBPRD
163  TMC_BASE_EPWM5->AQCSFRC |= (0x1<<2); // Forces a continuous low on output B
164  break;
165  case 10: TMC_BASE_EPWM6->CMPA = TMC_BASE_EPWM6->TBPRD; // Set CMPA = TBPRD
166  TMC_BASE_EPWM6->AQCSFRC |= 0x1; // Forces a continuous low on output A
167  break;
168  case 11: TMC_BASE_EPWM6->CMPB = TMC_BASE_EPWM6->TBPRD; // Set CMPB = TBPRD
169  TMC_BASE_EPWM6->AQCSFRC |= (0x1<<2); // Forces a continuous low on output B
170  break;
171  default: return -1;
172  }
173  return 0;
174 }

◆ init_ePWM()

int16 init_ePWM ( Uint16  gpio,
Uint32  frequency 
)

Configuration of GPIO as epwm.

Parameters
[in]1) GPIO pin as Uint16 --> valid value: 0-11
Returns
Result of operations as int16
--> 0 = operation successful
--> -1 = invalid value of GPIO pin --> -5 = invalid value of frequency

Definition at line 20 of file epwm.c.

20  {
21  TMPS_EPWM PWM; // Create variable for register-access
22  if((frequency > 1000000) || (frequency < 1145)){ // Check frequency
23  return -5;
24  }
25  else{
26  switch(gpio){ // Check GPIO-Input parameter
27  case 0 ... 1: PWM = TMC_BASE_EPWM1; // Assign Register-address to variable for register access
28  break;
29  case 2 ... 3: PWM = TMC_BASE_EPWM2; // Assign Register-address to variable for register access
30  break;
31  case 4 ... 5: PWM = TMC_BASE_EPWM3; // Assign Register-address to variable for register access
32  break;
33  case 6 ... 7: PWM = TMC_BASE_EPWM4; // Assign Register-address to variable for register access
34  break;
35  case 8 ... 9: PWM = TMC_BASE_EPWM5; // Assign Register-address to variable for register access
36  break;
37  case 10 ... 11: PWM = TMC_BASE_EPWM6; // Assign Register-address to variable for register access
38  break;
39  default: return -1;
40  }
41  EALLOW; // Allow register access
42  TMC_BASE_PIO->CTL[0].PUD &= ~((Uint32)0x1 << gpio); // Enable pull-up on GPIO
43  TMC_BASE_PIO->CTL[0].MUX1 |= ((Uint32)0x1 << gpio*2); // Configure GPIO as EPWM
44  TMC_BASE_SCR->PCLKCR0 &= ~(0x1 << 2); // Stop TBCLK (Time Base Clock) within each enabled ePWM module
45  EDIS; // Protect register
46 
47  PWM->TBPRD = (F_CPU/frequency)/2; // Set time-based period register
48  PWM->TBPHS = 0x0000; // Phase is 0
49  PWM->TBCTR = 0x0000; // Clear counter
50 
51  //Setup counter mode
52  PWM->TBCTL = 0x2; // UpDown Count mode
53  PWM->TBCTL &= ~(0x1 << 2); // Disable phase loading
54  PWM->TBCTL &= ~(0x1 << 3); // Load TBPRD from TB_SHADOW;
55  PWM->TBCTL |= (0x1 << 4); // Time-base counter equal to zero (TBCTR = 0x0000)
56  PWM->TBCTL &= ~(0x7 << 7); // Set Clock ratio to SYSCLKOUT
57  PWM->TBCTL &= ~(0x7 << 10); // Disable Time-base Clock Prescale
58 
59  // Set actions
60  PWM->AQCTLA = (0x2 << 4); // Set PWMxA on event A, up count
61  PWM->AQCTLA |= (0x1 << 6); // Clear PWMxA on event A, down count
62  PWM->AQCTLB = (0x2 << 8); // Set PWMxB on event B, up count
63  PWM->AQCTLB |= (0x1 << 10); // Clear PWMxB on event B, down count
64 
65  EALLOW;
66  TMC_BASE_SCR->PCLKCR0 |= (0x1 << 2); // All enabled ePWM module clocks are started with the first rising edge of TBCLK aligned.
67  EDIS;
68  }
69  return 0;
70 }
_TMS_EPWM::AQCTLA
TM_REG16 AQCTLA
Action Qualifier Control Register For Output A.
Definition: TMC_BASE_EPWM.h:28
_TMS_EPWM
ePWM Configuration and Control Registers (TMC_BASE_EPWM).
Definition: TMC_BASE_EPWM.h:16
_TMS_EPWM::TBCTL
TM_REG16 TBCTL
Time Base Control Register.
Definition: TMC_BASE_EPWM.h:17
_TMS_EPWM::TBPRD
TM_REG16 TBPRD
Time Base Period Register Set.
Definition: TMC_BASE_EPWM.h:22
Uint16
unsigned int Uint16
16 Bit Variable: 0 .. 65.535
Definition: global_defines.h:21
_TMS_EPWM::TBPHS
TM_REG16 TBPHS
Time Base Phase Register.
Definition: TMC_BASE_EPWM.h:20
_TMS_EPWM::TBCTR
TM_REG16 TBCTR
Time Base Counter Register.
Definition: TMC_BASE_EPWM.h:21
_TMS_EPWM::AQCTLB
TM_REG16 AQCTLB
Action Qualifier Control Register For Output B.
Definition: TMC_BASE_EPWM.h:29
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22