33 static int CAN_A_in_use=0;
34 static int CAN_B_in_use=0;
38 switch(CAN_Int.
canrx){
39 case 10:
if(!CAN_B_in_use){
40 TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
canrx);
41 TMC_BASE_PIO->CTL[0].QSEL1 |= ((
Uint32)0x3 << 20);
42 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 20);
43 switch(CAN_Int.
cantx){
44 case 8: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
45 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 16);
47 case 12: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
48 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 24);
50 case 16: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
51 TMC_BASE_PIO->CTL[0].MUX2 |= (0x2);
53 case 20: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
54 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 8);
65 case 13:
if(!CAN_B_in_use){
66 TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
canrx);
67 TMC_BASE_PIO->CTL[0].QSEL1 |= (0x3 << (CAN_Int.
canrx*2));
68 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 26);
69 switch(CAN_Int.
cantx){
70 case 8: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
71 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 16);
73 case 12: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
74 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 24);
76 case 16: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
77 TMC_BASE_PIO->CTL[0].MUX2 |= (0x2);
79 case 20: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
80 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 8);
91 case 17:
if(!CAN_B_in_use){
92 TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
canrx);
93 TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3 << 2);
94 TMC_BASE_PIO->CTL[0].MUX2 |= (0x2 << 2);
95 switch(CAN_Int.
cantx){
96 case 8: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
97 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 16);
99 case 12: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
100 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 24);
102 case 16: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
103 TMC_BASE_PIO->CTL[0].MUX2 |= (0x2);
105 case 20: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
106 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 8);
117 case 18:
if(!CAN_A_in_use){
118 TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
canrx);
119 TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3 << 4);
120 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 4);
121 switch(CAN_Int.
cantx){
122 case 19: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
123 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 6);
125 case 31: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
126 TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x1 << 30);
137 case 21:
if(!CAN_B_in_use){
138 TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
canrx);
139 TMC_BASE_PIO->CTL[0].QSEL2 |= (0x3 << 10);
140 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 10);
141 switch(CAN_Int.
cantx){
142 case 8: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
143 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 16);
145 case 12: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
146 TMC_BASE_PIO->CTL[0].MUX1 |= ((
Uint32)0x2 << 24);
148 case 16: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
149 TMC_BASE_PIO->CTL[0].MUX2 |= (0x2);
151 case 20: TMC_BASE_PIO->CTL[0].PUD &= ~(0x1 << CAN_Int.
cantx);
152 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 8);
163 case 30:
if(!CAN_A_in_use){
164 TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 << CAN_Int.
canrx);
165 TMC_BASE_PIO->CTL[0].QSEL2 |= ((
Uint32)0x3 << 28);
166 TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x1 << 28);
167 switch(CAN_Int.
cantx){
168 case 19: TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 << CAN_Int.
cantx);
169 TMC_BASE_PIO->CTL[0].MUX2 |= (0x3 << 6);
171 case 31: TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 << CAN_Int.
cantx);
172 TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x1 << 30);
190 CAN->
MC |= (0x1 << 10);
191 CAN->
MC |= (0x1 << 13);
193 TMC_BASE_SCR->PCLKCR0 |= (0x1 << 14);
203 return CAN_setBaudrate(CAN, baudrate);
224 struct timing act_setting = {0,1,2,2};
225 struct timing best_setting = {1000000,1,1,2};
229 brp = (F_CPU_HALF/(baudrate*(act_setting.phase1+act_setting.phase2+act_setting.prop+1)))-1;
230 rate = (F_CPU_HALF/((brp+1)*(act_setting.phase1+act_setting.phase2+act_setting.prop+1)));
231 if(rate!=baudrate) rate2 = (F_CPU_HALF/(((brp+1)+1)*(act_setting.phase1+act_setting.phase2+act_setting.prop+1)));
232 if((baudrate-rate2)<(rate-baudrate)) rate = rate2;
235 if(rate == baudrate){
236 best_setting.prop = act_setting.prop;
237 best_setting.phase1 = act_setting.phase1;
238 best_setting.phase2 = act_setting.phase2;
243 if(rate> baudrate) act_setting.rest = rate - baudrate;
244 else act_setting.rest = baudrate - rate;
246 if(act_setting.rest<best_setting.rest){
247 best_setting.rest = act_setting.rest;
248 best_setting.phase1 = act_setting.phase1;
249 best_setting.phase2 = act_setting.phase2;
250 best_setting.prop = act_setting.prop;
253 if(act_setting.prop==9){
255 act_setting.phase1++;
256 act_setting.phase2++;
257 if(act_setting.phase1==9) ok = 1;
261 return CAN_setBittiming(CAN, best_setting.prop+best_setting.phase1,best_setting.phase2, baudrate);
283 if(baudrate>1000000)
return -9;
284 if(tseg1<tseg2)
return -11;
285 if(tseg1>16)
return -12;
286 if(tseg2>8)
return -13;
287 if(tseg1<2)
return -14;
288 if(tseg2<1)
return -15;
290 brp = (F_CPU_HALF/(baudrate*(tseg1+tseg2+1)))-1;
291 rate1 = (F_CPU_HALF/((brp+1)*(tseg1+tseg2+1)));
292 if(rate1!=baudrate) rate2 = (F_CPU_HALF/(((brp+1)+1)*(tseg1+tseg2+1)));
293 if((baudrate-rate2)<(rate1-baudrate)){
298 if(brp>255)
return -8;
302 while(!(CAN->
ES&(1<<4)));
304 CAN->
BTC = (brp<<16)|((tseg1-1)<<3)|(tseg2-1)|(1<<8);
305 if(brp>=5) CAN->
BTC |= (1<<7);
307 CAN->
MC &= (~(1<<12));
308 while(CAN->
ES&(1<<4));
334 if(CAN->
MO[mb_number].
ID != temp) {
336 CAN->
ME &= ~((
Uint32)0x1<<mb_number);
337 CAN->
MO[mb_number].
ID = temp;
344 temp2 |= (1UL<<mb_number);
347 CAN->
MD &= ~((
Uint32)0x1<<mb_number);
351 temp1 |= (
Uint32)(CAN->
ME | (1<<mb_number));
354 CAN->
ME &= ~((
Uint32)0x1<<mb_number);
376 if(CAN->
MD & ((
Uint32)0x1<<mb_number)){
380 CAN->
MO[mb_number].
MDL = 0;
381 CAN->
MO[mb_number].
MDH = 0;
384 CAN->
MO[mb_number].
MDL |= (*data&0xFFFFFFFF);
386 CAN->
MO[mb_number].
MDL |= (*data&0xFFFFFFFF);
387 CAN->
MO[mb_number].
MDH |= (*data>>32)&0xFFFFFFFF;
390 if(CAN->
TA & ((
Uint32)0x1<<mb_number)){
391 CAN->
TA |= ((
Uint32)0x1<<mb_number);
422 return CAN->
RMP&(1<<mb_number)?1:0;
439 *data |= CAN->
MO[mb_number].
MDL;
442 *data |= CAN->
MO[mb_number].
MDL;
446 CAN->
RMP |= (1<<mb_number);
458 CAN->
RMP |= (1<<mb_number);
471 return (CAN->
ME & (1UL<<mb_number))?1:0;
485 for(i=0; i<32; i++) {
486 if(!(CAN->
ME & (1UL<<i))) {
504 if(CAN->
MO[mb_number].
ID>>31 != 0) {
513 data->
active = CAN->
ME&(1UL<<mb_number)?1:0;
526 case 8: CAN = TMC_BASE_CANB;
528 case 10: CAN = TMC_BASE_CANB;
530 case 12: CAN = TMC_BASE_CANB;
532 case 13: CAN = TMC_BASE_CANB;
534 case 16: CAN = TMC_BASE_CANB;
536 case 17: CAN = TMC_BASE_CANB;
538 case 18: CAN = TMC_BASE_CANA;
540 case 19: CAN = TMC_BASE_CANA;
542 case 20: CAN = TMC_BASE_CANB;
544 case 21: CAN = TMC_BASE_CANB;
546 case 30: CAN = TMC_BASE_CANA;
548 case 31: CAN = TMC_BASE_CANA;