TMS320F28335 Library  1.0
Documentation
Data Structures | Typedefs | Functions
i2c.h File Reference

Header file for I2C module. More...

Go to the source code of this file.

Data Structures

struct  _I2CInterface
 I2C Interface: Assign GPIOs to I2C module. More...
 
struct  _TMS_I2C_Reg
 I2C Register structure for slave receive and transmit operations. More...
 
struct  _I2CMSG_transmit
 I2C Transmit-Message structure. More...
 

Typedefs

typedef struct _I2CInterface I2CInterface
 I2C Interface: Assign GPIOs to I2C module. More...
 
typedef struct _TMS_I2C_Reg TMS_I2C_Reg
 I2C Register structure for slave receive and transmit operations. More...
 
typedef struct _TMS_I2C_Reg * TMPS_I2C_Reg
 
typedef struct _I2CMSG_transmit I2CMSG_transmit
 I2C Transmit-Message structure. More...
 

Functions

int16 init_I2CMasterMode (I2CInterface)
 Initialization of I2C Interface master mode. More...
 
int16 init_I2CSlaveMode (I2CInterface, Uint16)
 Initialization of I2C Interface slave mode. More...
 
int16 I2C_writeDataAsMaster (I2CMSG_transmit *)
 Send data in I2C master mode to slave. More...
 
int16 I2C_readDataAsMaster (I2CMSG_transmit *)
 Read data in I2C master mode from slave. More...
 

Detailed Description

Header file for I2C module.

Definition in file i2c.h.

Typedef Documentation

◆ I2CInterface

typedef struct _I2CInterface I2CInterface

I2C Interface: Assign GPIOs to I2C module.


◆ I2CMSG_transmit

typedef struct _I2CMSG_transmit I2CMSG_transmit

I2C Transmit-Message structure.


◆ TMPS_I2C_Reg

typedef struct _TMS_I2C_Reg * TMPS_I2C_Reg

◆ TMS_I2C_Reg

typedef struct _TMS_I2C_Reg TMS_I2C_Reg

I2C Register structure for slave receive and transmit operations.


Function Documentation

◆ I2C_readDataAsMaster()

int16 I2C_readDataAsMaster ( I2CMSG_transmit *  msg)

Read data in I2C master mode from slave.

Parameters
[in]1) Pointer to I2CMSG_transmit
Returns
int16
--> 0 = operation successful
--> -18 = I2C module is disabled

Definition at line 194 of file i2c.c.

194  {
195  int i=0;
196 
197  if(!(TMC_BASE_I2C->MDR & 0x0020)){
198  return -18; // Return -1: I2C module is disabled
199  }
200 
201  while(TMC_BASE_I2C->STR & 0x1000); // Wait for end of transmission
202 
203  TMC_BASE_I2C->MDR |= (0x1<<10); // Master mode
204  TMC_BASE_I2C->MDR |= (0x1<<9); // Transmitter mode
205  TMC_BASE_I2C->SAR = msg->SlaveAddress; // Setup slave address
206  TMC_BASE_I2C->CNT = msg->RegisterAddressLength; // Setup I2CCNT (number of bytes to send = Addresslength)
207 
208  if(msg->RegisterAddressLength == 2){
209  TMC_BASE_I2C->DXR = msg->RegisterAddressHigh; // Write Adress High to DXR
210  }
211  if(msg->RegisterAddressLength >= 1){
212  TMC_BASE_I2C->DXR = msg->RegisterAddressLow; // Write Adress Low to DXR
213  }
214 
215  TMC_BASE_I2C->MDR |= (0x1<<13); // Set STT to 1 --> I2C module generates a START-condition on the I2C-bus
216 
217  while((TMC_BASE_I2C->FFTX & 0x1F00) > 0); // Wait while not all Bytes have been sent (Transmit FIFO contains >0 bytes)
218 
219  TMC_BASE_I2C->CNT = msg->DataLength; // Set up I2CCNT for Receiving bytes
220  TMC_BASE_I2C->MDR &= ~(0x1<<9); // Receive mode
221  TMC_BASE_I2C->MDR |= (0x1<<11); // Send STOP-Condition after all data has been received
222  TMC_BASE_I2C->MDR |= (0x1<<13); // Send repeated start bit
223 
224  for(i=0; i < msg->DataLength; i++)
225  {
226  while(!(TMC_BASE_I2C->FFRX & 0x0080)){ // Wait for 1 or more byte in receive FIFO
227 
228  }
229  msg->Data[i] = TMC_BASE_I2C->DRR; // Get Data from Receive FIFO
230  __asm(" RPT #255 || NOP");
231  TMC_BASE_I2C->FFRX |= (0x1 << 6); // Clear flag
232  }
233 
234  return 0;
235 
236 }

◆ I2C_writeDataAsMaster()

int16 I2C_writeDataAsMaster ( I2CMSG_transmit *  msg)

Send data in I2C master mode to slave.

Parameters
[in]1) Pointer to I2CMSG_transmit
Returns
int16
--> 0 = operation successful
--> -18 = I2C module is disabled

Definition at line 143 of file i2c.c.

143  {
144  Uint32 i;
145 
146  if(!(TMC_BASE_I2C->MDR & 0x0020)){
147  return -18; // Return -1: I2C module is disabled
148  }
149 
150  while(TMC_BASE_I2C->STR & 0x1000); // Wait for end of transmission
151 
152  TMC_BASE_I2C->MDR |= (0x1<<10); // Master mode
153  TMC_BASE_I2C->MDR |= (0x1<<9); // Transmitter mode
154  TMC_BASE_I2C->SAR = msg->SlaveAddress; // Setup slave address
155  TMC_BASE_I2C->CNT = msg->DataLength+msg->RegisterAddressLength; // Setup I2CCNT (number of bytes to send = Datalength + Addresslength)
156 
157 
158  if(msg->RegisterAddressLength == 2){
159  TMC_BASE_I2C->DXR = msg->RegisterAddressHigh; // Write Adress High to DXR
160  }
161  if(msg->RegisterAddressLength >= 1){
162  TMC_BASE_I2C->DXR = msg->RegisterAddressLow; // Write Adress Low to DXR
163  }
164  for (i=0; i<msg->DataLength; i++)
165  {
166  TMC_BASE_I2C->DXR = *(msg->Data+i); // Write Data to DXR
167  }
168 
169  TMC_BASE_I2C->MDR |= (0x1<<11); // Setup STOP-Condition Bit
170  TMC_BASE_I2C->MDR |= (0x1<<13); // Generate START-condition on the I2C-bus and send data from DXR
171 
172  for(i=0; i<800; i++){
173  __asm(" RPT #255 || NOP"); // Wait for transmission
174  }
175 
176  while(TMC_BASE_I2C->STR & 0x1000); // While BB --> Wait for end of transmission
177 
178  if(TMC_BASE_I2C->FFTX & 0x1F00){ // If Transmit FIFO not empty
179  TMC_BASE_I2C->FFTX &= ~(0x1<<14); // Disable Transmit Fifo Mode
180  TMC_BASE_I2C->FFTX &= ~(0x1<<13); // Disable Transmit Fifo operation
181  TMC_BASE_I2C->FFTX |= (0x1<<14); // Enable Transmit Fifo Mode
182  TMC_BASE_I2C->FFTX |= (0x1<<13); // Enable Transmit Fifo operation
183  }
184  return 0;
185 }

◆ init_I2CMasterMode()

int16 init_I2CMasterMode ( I2CInterface  I2C)

Initialization of I2C Interface master mode.

Parameters
[in]1) I2CInterface I2C
Returns
int16
--> 0 = operation successful
--> -1 = I2C.sda invalid value
--> -2 = I2C.scl invalid value

Definition at line 23 of file i2c.c.

23  {
24  switch(I2C.sda){
25  case 32: switch(I2C.scl){
26  case 33: EALLOW;
27  TMC_BASE_PIO->CTL[1].PUD &= ~(0x1); // Enable pull-up for GPIO32 (SDAA)
28  TMC_BASE_PIO->CTL[1].QSEL1 &= ~(0x3<<0); // Synchronize to SYSCLKOUT GPIO32 (SDAA)
29  TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<0); // Configure GPIO32 to SDAA
30 
31  TMC_BASE_PIO->CTL[1].PUD &= ~(0x1); // Enable pull-up for GPIO33 (SCLA)
32  TMC_BASE_PIO->CTL[1].QSEL1 &= ~(0x3<<2); // Synchronize to SYSCLKOUT GPIO33 (SCLA)
33  TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<2); // Configure GPIO33 to SCLA
34  EDIS;
35 
36  TMC_BASE_I2C->MDR &= ~(0x0020); // Put module in reset
37 
38  TMC_BASE_I2C->PSC = 0xE; // Configure module clock to 10 MHz
39  TMC_BASE_I2C->CLKL = 35; // Clock low-time divide-down value --> 100 kHz on SCL
40  TMC_BASE_I2C->CLKH = 55; // Clock high-time divide-down value --> 100 kHz on SCL
41 
42  TMC_BASE_I2C->IER = (0x1 << 1); // Enable NACK interrupts
43  TMC_BASE_I2C->MDR |= (0x1<<10); // Set master mode
44 
45  TMC_BASE_I2C->FFTX |= (0x1<<14); // Enable Transmit Fifo Mode
46  TMC_BASE_I2C->FFTX |= (0x1<<13); // Enable Transmit Fifo operation
47 
48  TMC_BASE_I2C->FFRX |= (0x1<<13); // Enable Receive FIFO Operation
49  TMC_BASE_I2C->FFRX |= (0x1); // Set Flag when there is 1 or more Byte in Receive FIFO
50  TMC_BASE_I2C->FFRX |= (0x1 << 6); // clear RXFFINT Flag
51 
52  DINT; // Disable Interrupts
53  EALLOW; // Allow register-access
54  TMC_BASE_INT_REGS->I2CINT1A = (Uint32)&I2C_masterISR; // Configure interrupt
55  EDIS; // Protect register
56  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
57  TMC_BASE_PIE->GROUP[7].IER |= 0x1; // Enable I2CINT1A in the PIE: Group 8 interrupt 1
58  IER |= 0x0080; // Enable IER Block
59  EINT; // Enable Interrupts
60 
61  TMC_BASE_I2C->MDR |= (0x1 << 5); // Release I2C from reset --> I2C module is enabled.
62 
63  break;
64  default: return -2;
65  }
66  break;
67  default: return -1;
68  }
69  return 0;
70 }

◆ init_I2CSlaveMode()

int16 init_I2CSlaveMode ( I2CInterface  I2C,
Uint16  slave_address 
)

Initialization of I2C Interface slave mode.

Parameters
[in]1) I2CInterface I2C
2) Uint16 slave_address
Returns
int16
--> 0 = operation successful
--> -1 = I2C.sda invalid value
--> -2 = I2C.scl invalid value

Definition at line 81 of file i2c.c.

81  {
82  switch(I2C.sda){
83  case 32: switch(I2C.scl){
84  case 33: EALLOW;
85  TMC_BASE_PIO->CTL[1].PUD &= ~(0x1); // Enable pull-up for GPIO32 (SDAA)
86  TMC_BASE_PIO->CTL[1].QSEL1 |= (0x3<<0); // Asynch input GPIO32 (SDAA)
87  TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<0); // Configure GPIO32 to SDAA
88 
89  TMC_BASE_PIO->CTL[1].PUD &= ~(0x1<<1); // Enable pull-up for GPIO33 (SCLA)
90  TMC_BASE_PIO->CTL[1].QSEL1 |= (0x3<<2); // Asynch input GPIO33 (SCLA)
91  TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<2); // Configure GPIO33 to SCLA
92  EDIS;
93 
94  TMC_BASE_I2C->MDR &= ~(0x0020); // Put module in reset
95 
96  TMC_BASE_I2C->PSC = 0xE; // Configure module clock to 10 MHz
97  TMC_BASE_I2C->CLKL = 35; // Clock low-time divide-down value --> 100 kHz on SCL
98  TMC_BASE_I2C->CLKH = 55; // Clock high-time divide-down value --> 100 kHz on SCL
99  TMC_BASE_I2C->IER = (0x1 << 6); // Enable Adressed as Slave Interrupt
100 
101  TMC_BASE_I2C->FFTX |= (0x1<<14); // Enable Transmit Fifo Mode
102  TMC_BASE_I2C->FFTX |= (0x1<<13); // Enable Transmit Fifo operation
103  TMC_BASE_I2C->FFTX &= ~(0x1F); // Set Flag when Transmit FIFO is empty
104  TMC_BASE_I2C->FFTX |= (0x1 << 6); // clear TXFFINT Flag
105 
106  TMC_BASE_I2C->FFRX |= (0x1<<13); // Enable Receive FIFO Operation
107  TMC_BASE_I2C->FFRX |= (0x1); // Set Flag when there is 1 or more Byte in Receive FIFO
108  TMC_BASE_I2C->FFRX |= (0x1 << 6); // clear RXFFINT Flag
109 
110  TMC_BASE_I2C->OAR = slave_address; // 7 Bit slave address
111 
112  TMC_BASE_I2C->MDR &= ~(0x1<<3); // Free data format disabled
113  TMC_BASE_I2C->MDR &= ~(0x1<<8); // 7 bit address-mode
114  TMC_BASE_I2C->MDR &= ~(0x1<<10); // Slave mode
115 
116  DINT; // Disable Interrupts
117  EALLOW; // Allow register-access
118  TMC_BASE_INT_REGS->I2CINT1A = (Uint32)&I2C_slaveISR; // Configure interrupt
119  EDIS; // Protect register
120  TMC_BASE_PIE->CTRL |= 0x01; // Enable PIE block
121  TMC_BASE_PIE->GROUP[7].IER |= 0x1; // Enable I2CINT1A in the PIE: Group 8 interrupt 1
122  IER |= 0x0080; // Enable IER Block
123  EINT; // Enable Interrupts
124 
125  TMC_BASE_I2C->MDR |= 0x0020; // Release I2C from reset --> I2C module is enabled.
126 
127  break;
128  default: return -2;
129  }
130  break;
131  default: return -1;
132  }
133  return 0;
134 }
I2C_slaveISR
__interrupt void I2C_slaveISR(void)
I2C ISR-Routine in slave mode when Adressed detected.
Definition: i2c.c:265
IER
cregister volatile unsigned int IER
Generate reference to Interrupt Enable Register.
I2C_masterISR
__interrupt void I2C_masterISR(void)
I2C ISR-Routine in master mode when NACK detected.
Definition: i2c.c:243
_I2CInterface::scl
Uint16 scl
I2C-SCL-GPIO (GPIO33)
Definition: i2c.h:14
_I2CMSG_transmit::RegisterAddressLow
Uint16 RegisterAddressLow
Write second byte of Registeradress. Example: 0x12.
Definition: i2c.h:29
_I2CInterface::sda
Uint16 sda
I2C-SDA-GPIO (GPIO32)
Definition: i2c.h:13
_I2CMSG_transmit::RegisterAddressHigh
Uint16 RegisterAddressHigh
Write first byte of Registeradress. Example: 0xFF.
Definition: i2c.h:28
_I2CMSG_transmit::SlaveAddress
Uint16 SlaveAddress
Write 7-Bit Slave Adress. Example: 0x3.
Definition: i2c.h:26
_I2CMSG_transmit::RegisterAddressLength
Uint16 RegisterAddressLength
Write length of Registeradress in Byte(max. 2). Example: 2 (for 0xFF12)
Definition: i2c.h:27
_I2CMSG_transmit::Data
Uint16 Data[16]
Write data to be sent into Data-Array. Read Data from Array after Read-operations.
Definition: i2c.h:31
_I2CMSG_transmit::DataLength
Uint16 DataLength
Write length of databytes to receive or to transmit. Example: 2 (for transmission of 0x6688)
Definition: i2c.h:30
Uint32
unsigned long Uint32
32 Bit Variable: 0 .. 4.294.967.295
Definition: global_defines.h:22