i2c.c

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#include <register/TMC_BASE_I2C.h>
#include <register/TMC_BASE_INT_REGS.h>
#include <register/TMC_BASE_PIE.h>
#include <register/TMC_BASE_PIO.h>
#include <register/TMC_BASE_XINT.h>
#include "i2c.h"
 
__interrupt void I2C_masterISR(void);
__interrupt void I2C_slaveISR(void);
 
int16 init_I2CMasterMode(I2CInterface I2C){
    switch(I2C.sda){
        case 32:    switch(I2C.scl){
                        case 33:    EALLOW;
                                    TMC_BASE_PIO->CTL[1].PUD &= ~(0x1);         // Enable pull-up for GPIO32 (SDAA)
                                    TMC_BASE_PIO->CTL[1].QSEL1 &= ~(0x3<<0);    // Synchronize to SYSCLKOUT GPIO32 (SDAA)
                                    TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<0);      // Configure GPIO32 to SDAA
 
                                    TMC_BASE_PIO->CTL[1].PUD &= ~(0x1);         // Enable pull-up for GPIO33 (SCLA)
                                    TMC_BASE_PIO->CTL[1].QSEL1 &= ~(0x3<<2);    // Synchronize to SYSCLKOUT GPIO33 (SCLA)
                                    TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<2);      // Configure GPIO33 to SCLA
                                    EDIS;
 
                                    TMC_BASE_I2C->MDR &= ~(0x0020);             // Put module in reset
 
                                    TMC_BASE_I2C->PSC = 0xE;                    // Configure module clock to 10 MHz
                                    TMC_BASE_I2C->CLKL = 35;                    // Clock low-time divide-down value --> 100 kHz on SCL
                                    TMC_BASE_I2C->CLKH  = 55;                   // Clock high-time divide-down value --> 100 kHz on SCL
 
                                    TMC_BASE_I2C->IER = (0x1 << 1);             // Enable NACK interrupts
                                    TMC_BASE_I2C->MDR |= (0x1<<10);             // Set master mode
 
                                    TMC_BASE_I2C->FFTX |= (0x1<<14);            // Enable Transmit Fifo Mode
                                    TMC_BASE_I2C->FFTX |= (0x1<<13);            // Enable Transmit Fifo operation
 
                                    TMC_BASE_I2C->FFRX |= (0x1<<13);            // Enable Receive FIFO Operation
                                    TMC_BASE_I2C->FFRX |= (0x1);                // Set Flag when there is 1 or more Byte in Receive FIFO
                                    TMC_BASE_I2C->FFRX |= (0x1 << 6);           // clear RXFFINT Flag
 
                                    DINT;                                                       // Disable Interrupts
                                    EALLOW;                                                     // Allow register-access
                                    TMC_BASE_INT_REGS->I2CINT1A = (Uint32)&I2C_masterISR;       // Configure interrupt
                                    EDIS;                                                       // Protect register
                                    TMC_BASE_PIE->CTRL |= 0x01;                                 // Enable PIE block
                                    TMC_BASE_PIE->GROUP[7].IER |= 0x1;                          // Enable I2CINT1A in the PIE: Group 8 interrupt 1
                                    IER |= 0x0080;                                              // Enable IER Block
                                    EINT;                                                       // Enable Interrupts
 
                                    TMC_BASE_I2C->MDR |= (0x1 << 5);                            // Release I2C from reset --> I2C module is enabled.
 
                                    break;
                        default:    return -2;
                    }
                    break;
        default:    return -1;
    }
    return 0;
}
 
int16 init_I2CSlaveMode(I2CInterface I2C, Uint16 slave_address){
    switch(I2C.sda){
        case 32:    switch(I2C.scl){
                        case 33:    EALLOW;
                                    TMC_BASE_PIO->CTL[1].PUD &= ~(0x1);         // Enable pull-up for GPIO32 (SDAA)
                                    TMC_BASE_PIO->CTL[1].QSEL1 |= (0x3<<0);     // Asynch input GPIO32 (SDAA)
                                    TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<0);      // Configure GPIO32 to SDAA
 
                                    TMC_BASE_PIO->CTL[1].PUD &= ~(0x1<<1);      // Enable pull-up for GPIO33 (SCLA)
                                    TMC_BASE_PIO->CTL[1].QSEL1 |= (0x3<<2);     // Asynch input GPIO33 (SCLA)
                                    TMC_BASE_PIO->CTL[1].MUX1 |= (0x1<<2);      // Configure GPIO33 to SCLA
                                    EDIS;
 
                                    TMC_BASE_I2C->MDR &= ~(0x0020);             // Put module in reset
 
                                    TMC_BASE_I2C->PSC = 0xE;                    // Configure module clock to 10 MHz
                                    TMC_BASE_I2C->CLKL = 35;                    // Clock low-time divide-down value --> 100 kHz on SCL
                                    TMC_BASE_I2C->CLKH  = 55;                   // Clock high-time divide-down value --> 100 kHz on SCL
                                    TMC_BASE_I2C->IER = (0x1 << 6);             // Enable Adressed as Slave Interrupt
 
                                    TMC_BASE_I2C->FFTX |= (0x1<<14);            // Enable Transmit Fifo Mode
                                    TMC_BASE_I2C->FFTX |= (0x1<<13);            // Enable Transmit Fifo operation
                                    TMC_BASE_I2C->FFTX &= ~(0x1F);              // Set Flag when Transmit FIFO is empty
                                    TMC_BASE_I2C->FFTX |= (0x1 << 6);           // clear TXFFINT Flag
 
                                    TMC_BASE_I2C->FFRX |= (0x1<<13);            // Enable Receive FIFO Operation
                                    TMC_BASE_I2C->FFRX |= (0x1);                // Set Flag when there is 1 or more Byte in Receive FIFO
                                    TMC_BASE_I2C->FFRX |= (0x1 << 6);           // clear RXFFINT Flag
 
                                    TMC_BASE_I2C->OAR = slave_address;          // 7 Bit slave address
 
                                    TMC_BASE_I2C->MDR &= ~(0x1<<3);             // Free data format disabled
                                    TMC_BASE_I2C->MDR &= ~(0x1<<8);             // 7 bit address-mode
                                    TMC_BASE_I2C->MDR &= ~(0x1<<10);            // Slave mode
 
                                    DINT;                                                           // Disable Interrupts
                                    EALLOW;                                                         // Allow register-access
                                    TMC_BASE_INT_REGS->I2CINT1A = (Uint32)&I2C_slaveISR;            // Configure interrupt
                                    EDIS;                                                           // Protect register
                                    TMC_BASE_PIE->CTRL |= 0x01;                                     // Enable PIE block
                                    TMC_BASE_PIE->GROUP[7].IER |= 0x1;                              // Enable I2CINT1A in the PIE: Group 8 interrupt 1
                                    IER |= 0x0080;                                                  // Enable IER Block
                                    EINT;                                                           // Enable Interrupts
 
                                    TMC_BASE_I2C->MDR |= 0x0020;                // Release I2C from reset --> I2C module is enabled.
 
                                    break;
                        default:    return -2;
                    }
                    break;
        default:    return -1;
    }
    return 0;
}
 
int16 I2C_writeDataAsMaster(I2CMSG_transmit *msg){
    Uint32 i;
 
    if(!(TMC_BASE_I2C->MDR & 0x0020)){
        return -18;                                                             // Return -1: I2C module is disabled
    }
 
    while(TMC_BASE_I2C->STR & 0x1000);                                          // Wait for end of transmission
 
    TMC_BASE_I2C->MDR |= (0x1<<10);                                             // Master mode
    TMC_BASE_I2C->MDR |= (0x1<<9);                                              // Transmitter mode
    TMC_BASE_I2C->SAR = msg->SlaveAddress;                                      // Setup slave address
    TMC_BASE_I2C->CNT = msg->DataLength+msg->RegisterAddressLength;             // Setup I2CCNT (number of bytes to send = Datalength + Addresslength)
 
 
    if(msg->RegisterAddressLength == 2){
        TMC_BASE_I2C->DXR = msg->RegisterAddressHigh;                           // Write Adress High to DXR
    }
    if(msg->RegisterAddressLength >= 1){
        TMC_BASE_I2C->DXR = msg->RegisterAddressLow;                            // Write Adress Low to DXR
    }
    for (i=0; i<msg->DataLength; i++)
    {
        TMC_BASE_I2C->DXR = *(msg->Data+i);                                     // Write Data to DXR
    }
 
    TMC_BASE_I2C->MDR |= (0x1<<11);                                             // Setup STOP-Condition Bit
    TMC_BASE_I2C->MDR |= (0x1<<13);                                             // Generate START-condition on the I2C-bus and send data from DXR
 
    for(i=0; i<800; i++){
        __asm(" RPT #255 || NOP");                                              // Wait for transmission
    }
 
    while(TMC_BASE_I2C->STR & 0x1000);                                          // While BB --> Wait for end of transmission
 
    if(TMC_BASE_I2C->FFTX & 0x1F00){                                            // If Transmit FIFO not empty
        TMC_BASE_I2C->FFTX &= ~(0x1<<14);                                       // Disable Transmit Fifo Mode
        TMC_BASE_I2C->FFTX &= ~(0x1<<13);                                       // Disable Transmit Fifo operation
        TMC_BASE_I2C->FFTX |= (0x1<<14);                                        // Enable Transmit Fifo Mode
        TMC_BASE_I2C->FFTX |= (0x1<<13);                                        // Enable Transmit Fifo operation
    }
    return 0;
}
 
int16 I2C_readDataAsMaster(I2CMSG_transmit *msg){
    int i=0;
 
    if(!(TMC_BASE_I2C->MDR & 0x0020)){
        return -18;                                                              // Return -1: I2C module is disabled
    }
 
    while(TMC_BASE_I2C->STR & 0x1000);                                          // Wait for end of transmission
 
    TMC_BASE_I2C->MDR |= (0x1<<10);                                             // Master mode
    TMC_BASE_I2C->MDR |= (0x1<<9);                                              // Transmitter mode
    TMC_BASE_I2C->SAR = msg->SlaveAddress;                                      // Setup slave address
    TMC_BASE_I2C->CNT = msg->RegisterAddressLength;                             // Setup I2CCNT (number of bytes to send = Addresslength)
 
    if(msg->RegisterAddressLength == 2){
        TMC_BASE_I2C->DXR = msg->RegisterAddressHigh;                           // Write Adress High to DXR
    }
    if(msg->RegisterAddressLength >= 1){
        TMC_BASE_I2C->DXR = msg->RegisterAddressLow;                            // Write Adress Low to DXR
    }
 
    TMC_BASE_I2C->MDR |= (0x1<<13);                                             // Set STT to 1 --> I2C module generates a START-condition on the I2C-bus
 
    while((TMC_BASE_I2C->FFTX & 0x1F00) > 0);                                   // Wait while not all Bytes have been sent (Transmit FIFO contains >0 bytes)
 
    TMC_BASE_I2C->CNT = msg->DataLength;                                        // Set up I2CCNT for Receiving bytes
    TMC_BASE_I2C->MDR &= ~(0x1<<9);                                             // Receive mode
    TMC_BASE_I2C->MDR |= (0x1<<11);                                             // Send STOP-Condition after all data has been received
    TMC_BASE_I2C->MDR |= (0x1<<13);                                             // Send repeated start bit
 
    for(i=0; i < msg->DataLength; i++)
    {
        while(!(TMC_BASE_I2C->FFRX & 0x0080)){                                  // Wait for 1 or more byte in receive FIFO
 
        }
        msg->Data[i] = TMC_BASE_I2C->DRR;                                       // Get Data from Receive FIFO
        __asm(" RPT #255 || NOP");
        TMC_BASE_I2C->FFRX |= (0x1 << 6);                                       // Clear flag
    }
 
    return 0;
 
}
 
__interrupt void I2C_masterISR(void){
    //NACK detected --> abort transmission and release bus
    do{
        TMC_BASE_I2C->MDR &= ~(0x1 << 5);                                       // Release Bus (sets Bus Busy to 0)
        TMC_BASE_I2C->MDR |= (0x1 << 5);
 
        TMC_BASE_I2C->FFTX &= ~(0x1<<14);                                       // Disable Transmit FIFO Mode
        TMC_BASE_I2C->FFTX &= ~(0x1<<13);                                       // Disable Transmit FIFO operation
        TMC_BASE_I2C->FFTX |= (0x1<<14);                                        // Enable Transmit FIFO Mode
        TMC_BASE_I2C->FFTX |= (0x1<<13);                                        // Enable Transmit FIFO operation
    }
    while(TMC_BASE_I2C->STR & 0x1000);
    TMC_BASE_PIE->ACK |= 0x0080;                                                // Enable future I2C (PIE Group 8) interrupts
}
 
__interrupt void I2C_slaveISR(void)
{
    TMPS_I2C_Reg TMC_BASE_I2C_register;
    Uint16 IntSource;
    Uint32 i=0;
    Uint16 z=0;
    static Uint16 previous_register_address = 0x0000;
    Uint16 register_address = 0x0000;
    Uint16 register_value = 0x0000;
    Uint16 stop = 0;
 
    IntSource = (TMC_BASE_I2C->ISRC & 0x0007);                                  // Read interrupt source and clear it via CPU read
    if(IntSource == 7)                                                          // Interrupt source = addressed as slave
    {
        for(i=0; i<2; i++){
            while(!(TMC_BASE_I2C->FFRX & 0x0080) && !stop){                     // Wait, while no byte in receive FIFO
                if(TMC_BASE_I2C->STR & 0x0020){                                 // break if Stop condition detected
                    stop=1;
                    break;
                }
            }
            if(stop){
                break;
            }
            register_address |= TMC_BASE_I2C->DRR;                              // Read byte from Rx-FIFO
            if(i==0){
                register_address = (register_address<<8);                       // Shift High Address Byte
            }
            TMC_BASE_I2C->FFRX |= (0x1 << 6);                                   // Clear Flag
            for (z=0;z<50;z++){
                __asm(" RPT #255 || NOP");
            }
        }
 
        if(!(TMC_BASE_I2C->STR & 0x4000)){                                      // If not Addressed as Slave Transmitter
            TMC_BASE_I2C_register = (TM_CAST(TMPS_I2C_Reg) register_address);   // Cast Addressbytes for register-access
            for(i=0; i<2; i++){
                while(!(TMC_BASE_I2C->FFRX & 0x0080) && !stop){                 // Wait, while no byte in receive FIFO
                    if(TMC_BASE_I2C->STR & 0x0020){                             // Break if Stop condition detected
                        stop=1;
                        break;
                    }
                }
                if(stop){
                    break;
                }
                if(i==0){
                    register_value = (Uint16) (TMC_BASE_I2C->DRR);              // Receive first Databyte
                }
                else{
                    register_value |= ((Uint16) TMC_BASE_I2C->DRR<<8);          // Receive second databyte
                    TMC_BASE_I2C_register->register_adress = register_value;    // Write datavalue into register
                    break;
                }
                TMC_BASE_I2C->FFRX |= (0x1 << 6);                               // Clear Flag
                for (z=0;z<50;z++){
                    __asm(" RPT #255 || NOP");
                }
            }
        }
        else{
            TMC_BASE_I2C_register = (TM_CAST(TMPS_I2C_Reg) previous_register_address);  // Cast Addressbytes for register-access
            TMC_BASE_I2C->MDR |= (0x1<<9);                                              // Transmitter mode
            TMC_BASE_I2C->DXR = ((TMC_BASE_I2C_register->register_adress) >> 8);        // Slave writes data to bus
            TMC_BASE_I2C->DXR = (TMC_BASE_I2C_register->register_adress);               // Slave writes data to bus
            while(TMC_BASE_I2C->FFTX & 0x0080){                                         // wait, while no byte in transmit FIFO
                if(TMC_BASE_I2C->STR & 0x0020){                                         // break if Stop condition detected
                    TMC_BASE_I2C->MDR &= ~(0x1<<9);                                     // Receiver mode
                    break;
                }
            }
            TMC_BASE_I2C->MDR &= ~(0x1<<9);                                             // Receiver mode
        }
    }
    else
    {
        __asm("   ESTOP0");                                                             // Generate some error due to invalid interrupt source
    }
    previous_register_address = register_address;
    TMC_BASE_PIE->ACK |= 0x0080;                                                        // Enable future I2C (PIE Group 8) interrupts
}