36         case 20:    
switch(eQEP.
QEPB){
 
   38                                     TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 << 20);       
 
   39                                     TMC_BASE_PIO->CTL[0].QSEL2 &= ~((
Uint32)0x3 << 8);      
 
   40                                     TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x1 << 8);        
 
   41                                     TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 << 21);       
 
   42                                     TMC_BASE_PIO->CTL[0].QSEL2 &= ~((
Uint32)0x3 << 10);     
 
   43                                     TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x1 << 10);       
 
   52                     TMC_BASE_PIE->CTRL |= 0x01;                                             
 
   53                     TMC_BASE_PIE->GROUP[4].IER |= 0x1;                                      
 
   56                     eQEP_module = TMC_BASE_EQEP1;                                           
 
   58         case 24:    
switch(eQEP.
QEPB){
 
   60                                     TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 << 24);       
 
   61                                     TMC_BASE_PIO->CTL[0].QSEL2 &= ~((
Uint32)0x3 << 16);     
 
   62                                     TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x2 << 16);       
 
   63                                     TMC_BASE_PIO->CTL[0].PUD &= ~((
Uint32)0x1 <<25);        
 
   64                                     TMC_BASE_PIO->CTL[0].QSEL2 &= ~((
Uint32)0x3 << 18);     
 
   65                                     TMC_BASE_PIO->CTL[0].MUX2 |= ((
Uint32)0x2 << 18);       
 
   74                     TMC_BASE_PIE->CTRL |= 0x01;                         
 
   75                     TMC_BASE_PIE->GROUP[4].IER |= 0x2;                  
 
   78                     eQEP_module = TMC_BASE_EQEP2;                       
 
   85     eQEP_module->
QUPRD = 0xE4E1C0;                  
 
   89     eQEP_module->
QPOSMAX = 0xFFFFFFFF;              
 
   90     eQEP_module->
QEPCTL |= (0x1 << 12);             
 
   91     eQEP_module->
QEPCTL |= (0x1 << 3);              
 
   92     eQEP_module->
QEPCTL |= (0x1 << 2);              
 
   93     eQEP_module->
QEPCTL |= (0x1 << 1);              
 
   95     eQEP_module->
QEINT &= ~(0xFFE);                 
 
   97     eQEP_module->
QCLR |= 0xFFF;                     
 
  112     if(eQEP.
QEPA == GPIO20){
 
  113         eQEP_module = TMC_BASE_EQEP1;               
 
  115     else if(eQEP.
QEPA == GPIO24){
 
  116         eQEP_module = TMC_BASE_EQEP2;               
 
  121     return ((eQEP_module->
QEPSTS >> 5)& 0x1);       
 
  132     if(eQEP.
QEPA == GPIO20){
 
  135     else if(eQEP.
QEPA == GPIO24){
 
  152     signed long pos_diff=0;
 
  160     if(eQEP_module->
QEPSTS & 0x20){                 
 
  161         pos_diff = (
signed long)(pos[1] - pos[0]);  
 
  163             pos_diff += 0xFFFFFFFF;                 
 
  167         pos_diff = (
signed long)(pos[0] - pos[1]);  
 
  169             pos_diff += 0xFFFFFFFF;                 
 
  173     counts_per_sec = pos_diff * 10;                                                     
 
  177     eQEP_module->
QCLR |= 0xFFF;                                                         
 
  178     TMC_BASE_PIE->ACK |= 0x0010;                                                        
 
  190     signed long pos_diff=0;
 
  198     if(eQEP_module->
QEPSTS & 0x20){                 
 
  199         pos_diff = (
signed long)(pos[1] - pos[0]);  
 
  201             pos_diff += 0xFFFFFFFF;                 
 
  205         pos_diff = (
signed long)(pos[0] - pos[1]);  
 
  207             pos_diff += 0xFFFFFFFF;                 
 
  211     counts_per_sec = pos_diff * 10;                                                     
 
  215     eQEP_module->
QCLR |= 0xFFF;                                                         
 
  216     TMC_BASE_PIE->ACK |= 0x10;