Data Structures

Here are the data structures with brief descriptions:

C_CanInterface	CAN Interface: Assign GPIOs to CAN_A or CAN_B
C_CanMailbox	CAN Mailbox Strucutre for instantiation of CAN-Mailboxes
C_eQEPInterface	EQEP Interface: Assign GPIOs to TMC_BASE_EQEP1 or TMC_BASE_EQEP2
C_I2CInterface	I2C Interface: Assign GPIOs to I2C module
C_I2CMSG_transmit	I2C Transmit-Message structure
C_SCIInterface	SCI Interface: Assign GPIOs and baudrate to SCI_A / SCI_B / SCI_C
C_SPIInterface	SPI Interface: Assign GPIOs to SPI module
C_TMS_ADC	ADC Registers (TMC_BASE_ADC)
C_TMS_ADC_RESULT	ADC Conversion Result Buffer Register (TMC_BASE_ADC_RESULT)
C_TMS_CAN	CAN Register (TMC_BASE_CANA / TMC_BASE_CANB)
C_TMS_CAN_MO	CAN Mailbox for send and receive operations
C_TMS_ECAP	ECAP Register (TMC_BASE_ECAP1 - TMC_BASE_ECAP6)
C_TMS_EPWM	EPWM Configuration and Control Registers (TMC_BASE_EPWM)
C_TMS_EQEP	EQEP Register (TMC_BASE_EQEP1 / TMC_BASE_EQEP2)
C_TMS_I2C	I2C Registers (TMC_BASE_I2C)
C_TMS_I2C_Reg	I2C Register structure for slave receive and transmit operations
C_TMS_INT_REGS	PIE Vector Table Group 1-12 Interrupts (TMC_BASE_INT_REGS)
C_TMS_PIE	PIE Configuration and Control Registers (TMC_BASE_PIE)
C_TMS_PIE_GROUP	PIE Configuration and Control Registers (TMC_BASE_PIE)
C_TMS_PIO	GPIO Control Registers (TMC_BASE_PIO)
C_TMS_PIO_CTL	GPIO Control Registers (TMC_BASE_PIO)
C_TMS_PIO_DATA	GPIO Control Registers (TMC_BASE_PIO)
C_TMS_SCI	SCI Register (TMC_BASE_SCIA / TMC_BASE_SCIB / TMC_BASE_SCIC)
C_TMS_SCR	PLL, Clocking, Watchdog, and Low-Power Mode Registers (TMC_BASE_SCR)
C_TMS_SPI	SPI Register (TMC_BASE_SPIA)
C_TMS_TIM_INT_REGS	PIE-Vector-Table for CPU-TIMER1 and CPU-TIMER2 (TMC_TIM_INT_REGS)
C_TMS_TIMER	32-Bit CPU Timers 0/1/2 (TMC_BASE_TIMER)
C_TMS_XINT	External Interrupt Control Registers (TMC_BASE_XINT)